src/mainboard/tyan/s8226/buildOpts.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <stdlib.h>
  17
  18 #include "AGESA.h"
  19 #include "AdvancedApi.h"
  20
  21 /* AGESA will check the OEM configuration during preprocessing stage,
  22  * coreboot enable -Wundef option, so we should make sure we have all contanstand defined
  23  */
  24 /* MEMORY_BUS_SPEED */
  25 #define DDR400_FREQUENCY                200     ///< DDR 400
  26 #define DDR533_FREQUENCY                266     ///< DDR 533
  27 #define DDR667_FREQUENCY                333     ///< DDR 667
  28 #define DDR800_FREQUENCY                400     ///< DDR 800
  29 #define DDR1066_FREQUENCY               533     ///< DDR 1066
  30 #define DDR1333_FREQUENCY               667     ///< DDR 1333
  31 #define DDR1600_FREQUENCY               800     ///< DDR 1600
  32 #define DDR1866_FREQUENCY               933     ///< DDR 1866
  33 #define UNSUPPORTED_DDR_FREQUENCY       934     ///< Highest limit of DDR frequency
  34
  35 /* QUANDRANK_TYPE*/
  36 #define QUADRANK_REGISTERED             0       ///< Quadrank registered DIMM
  37 #define QUADRANK_UNBUFFERED             1       ///< Quadrank unbuffered DIMM
  38
  39 /* USER_MEMORY_TIMING_MODE */
  40 #define TIMING_MODE_AUTO                0       ///< Use best rate possible
  41 #define TIMING_MODE_LIMITED             1       ///< Set user top limit
  42 #define TIMING_MODE_SPECIFIC            2       ///< Set user specified speed
  43
  44 /* POWER_DOWN_MODE */
  45 #define POWER_DOWN_BY_CHANNEL           0       ///< Channel power down mode
  46 #define POWER_DOWN_BY_CHIP_SELECT       1       ///< Chip select power down mode
  47
  48 /* User makes option selections here
  49  * Comment out the items wanted to be included in the build.
  50  * Uncomment those items you with to REMOVE from the build.
  51  */
  52 //#define BLDOPT_REMOVE_UDIMMS_SUPPORT           TRUE
  53 //#define BLDOPT_REMOVE_RDIMMS_SUPPORT           TRUE
  54 //#define BLDOPT_REMOVE_ECC_SUPPORT              TRUE
  55 //#define BLDOPT_REMOVE_BANK_INTERLEAVE          TRUE
  56 //#define BLDOPT_REMOVE_DCT_INTERLEAVE           TRUE
  57 //#define BLDOPT_REMOVE_NODE_INTERLEAVE          TRUE
  58 //#define BLDOPT_REMOVE_PARALLEL_TRAINING        TRUE
  59 //#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT     TRUE
  60 #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT      TRUE
  61 //#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT      TRUE
  62 ////#define BLDOPT_REMOVE_ACPI_PSTATES             TRUE
  63 ////#define BLDOPT_REMOVE_SRAT                     TRUE
  64 ////#define BLDOPT_REMOVE_SLIT                     TRUE
  65 //#define BLDOPT_REMOVE_WHEA                     TRUE
  66 //#define BLDOPT_REMOVE_DMI                      TRUE
  67
  68 /*f15 Rev A1 ucode patch CpuF15OrMicrocodePatch0600011F */
  69 #define BLDOPT_REMOVE_EARLY_SAMPLES             FALSE
  70
  71 //#define BLDOPT_REMOVE_HT_ASSIST                TRUE
  72 //#define BLDOPT_REMOVE_MSG_BASED_C1E            TRUE
  73 //#define BLDCFG_REMOVE_ACPI_PSTATES_PPC               TRUE
  74 //#define BLDCFG_REMOVE_ACPI_PSTATES_PCT               TRUE
  75 //#define BLDCFG_REMOVE_ACPI_PSTATES_PSD               TRUE
  76 //#define BLDCFG_REMOVE_ACPI_PSTATES_PSS               TRUE
  77 //#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS              TRUE
  78
  79 /* Build configuration values here.
  80  */
  81 #define BLDCFG_VRM_CURRENT_LIMIT                 120000
  82 #define BLDCFG_VRM_LOW_POWER_THRESHOLD           0
  83 #define BLDCFG_VRM_INRUSH_CURRENT_LIMIT          0
  84 #define BLDCFG_PLAT_NUM_IO_APICS                 3
  85 #define BLDCFG_CORE_LEVELING_MODE                CORE_LEVEL_LOWEST
  86 #define BLDCFG_MEM_INIT_PSTATE                   0
  87 #define BLDCFG_AMD_PSTATE_CAP_VALUE              0
  88
  89 #define BLDCFG_AMD_PLATFORM_TYPE                  AMD_PLATFORM_SERVER
  90
  91 #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT         DDR1333_FREQUENCY//1600
  92 #define BLDCFG_MEMORY_MODE_UNGANGED               TRUE
  93 #define BLDCFG_MEMORY_QUAD_RANK_CAPABLE           TRUE
  94 #define BLDCFG_MEMORY_QUADRANK_TYPE               QUADRANK_REGISTERED
  95 #define BLDCFG_MEMORY_RDIMM_CAPABLE               TRUE
  96 #define BLDCFG_MEMORY_UDIMM_CAPABLE               TRUE
  97 #define BLDCFG_MEMORY_SODIMM_CAPABLE              FALSE
  98 #define BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB          TRUE
  99 #define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING    FALSE//TRUE
 100 #define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING    FALSE//TRUE
 101 #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING        FALSE//TRUE
 102 #define BLDCFG_MEMORY_POWER_DOWN                  FALSE
 103 #define BLDCFG_POWER_DOWN_MODE                    POWER_DOWN_BY_CHANNEL
 104 #define BLDCFG_ONLINE_SPARE                       FALSE
 105 #define BLDCFG_BANK_SWIZZLE                       TRUE
 106 #define BLDCFG_TIMING_MODE_SELECT                 TIMING_MODE_AUTO
 107 #define BLDCFG_MEMORY_CLOCK_SELECT                DDR1333_FREQUENCY //DDR800_FREQUENCY
 108 #define BLDCFG_DQS_TRAINING_CONTROL               TRUE
 109 #define BLDCFG_IGNORE_SPD_CHECKSUM                FALSE
 110 #define BLDCFG_USE_BURST_MODE                     FALSE
 111 #define BLDCFG_MEMORY_ALL_CLOCKS_ON               FALSE
 112 #define BLDCFG_ENABLE_ECC_FEATURE                 TRUE
 113 #define BLDCFG_ECC_REDIRECTION                    FALSE
 114 #define BLDCFG_SCRUB_IC_RATE                      0
 115 #define BLDCFG_ECC_SYNC_FLOOD                     TRUE
 116 #define BLDCFG_ECC_SYMBOL_SIZE                    4
 117
 118 #define BLDCFG_PCI_MMIO_BASE                    CONFIG_MMCONF_BASE_ADDRESS
 119 #define BLDCFG_PCI_MMIO_SIZE                    CONFIG_MMCONF_BUS_NUMBER
 120
 121 /**
 122  * Enable Message Based C1e CPU feature in multi-socket systems.
 123  * BLDCFG_PLATFORM_C1E_OPDATA element be defined with a valid IO port value,
 124  * else the feature cannot be enabled.
 125  */
 126 #define BLDCFG_PLATFORM_C1E_MODE                  C1eModeMsgBased
 127 #define BLDCFG_PLATFORM_C1E_OPDATA                0x80//TODO
 128 //#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1        0
 129 //#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2        0
 130
 131 #define BLDCFG_HEAP_DRAM_ADDRESS                  0xB0000
 132 #define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS    0xD0000000
 133 #define BLDCFG_1GB_ALIGN                          FALSE
 134 //#define BLDCFG_PROCESSOR_SCOPE_NAME0              'C'
 135 //#define BLDCFG_PROCESSOR_SCOPE_NAME1              '0'
 136 //
 137
 138 // Select the platform control flow mode for performance tuning.
 139 #define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm
 140
 141 /**
 142  * Enable the probe filtering performance tuning feature.
 143  * The probe filter provides filtering of broadcast probes to
 144  * improve link bandwidth and performance for multi- node systems.
 145  *
 146  * This feature may interact with other performance features.
 147  *  TRUE  -Enable the feature (default) if supported by all processors,
 148  *         based on revision and presence of L3 cache.
 149  *         The feature is not enabled if there are no coherent HT links.
 150  *  FALSE -Do not enable the feature regardless of the configuration.
 151  */
 152 //TODO enable it,
 153 //but AGESA set PFMode = 0; //PF Disable, HW never set PFInitDone
 154 //hang in F10HtAssistInit() do{...} while(PFInitDone != 1)
 155 #define BLDCFG_USE_HT_ASSIST    FALSE
 156
 157 /**
 158  * The socket and link match values are platform specific
 159  */
 160 CONST MANUAL_BUID_SWAP_LIST ROMDATA s8226_manual_swaplist[2] =
 161 {
 162         {
 163                 /* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */
 164                 HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
 165
 166                 { //BUID Swap List
 167                         { //BUID Swaps
 168                                 /* Each Non-coherent chain may have a list of device swaps,
 169                                  * Each item specify a device will be swap from its current id to a new one
 170                                  */
 171                                 /* FromID 0x00 is the chain with the southbridge */
 172                                 /* 'Move' device zero to device zero, All others are non applicable */
 173                                 {0x00, 0x00}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
 174                                 {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
 175                                 {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
 176                                 {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
 177                                 {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
 178                                 {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
 179                                 {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
 180                                 {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF},
 181                         },
 182
 183                         { //The ordered final BUIDs
 184                                 /* Specify the final BUID to be zero, All others are non applicable */
 185                                 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
 186                                 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
 187                                 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
 188                                 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
 189                         }
 190                 }
 191         },
 192
 193         /* The 2nd element in the array merely terminates the list */
 194         {
 195                 HT_LIST_TERMINAL,
 196         }
 197 };
 198
 199 #define HYPERTRANSPORT_V31_SUPPORT 1
 200
 201 #if HYPERTRANSPORT_V31_SUPPORT
 202 /**
 203  * The socket and link match values are platform specific
 204  *
 205  */
 206 CONST CPU_TO_CPU_PCB_LIMITS ROMDATA s8226_cpu2cpu_limit_list[2] =
 207 {
 208         {
 209                 /* On the reference platform, these settings apply to all coherent links */
 210                 HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
 211
 212                 /* Set incoming and outgoing links to 16 bit widths, and 3.2GHz frequencies */
 213                 HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_3200M,
 214         },
 215
 216         /* The 2nd element in the array merely terminates the list */
 217         {
 218                 HT_LIST_TERMINAL,
 219         }
 220 };
 221
 222 CONST IO_PCB_LIMITS ROMDATA s8226_io_limit_list[2] =
 223 {
 224         {
 225                 /* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */
 226                 HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
 227
 228                 /* Set upstream and downstream links to 16 bit widths, and limit frequencies to 3.2GHz */
 229                 HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_3200M, //Actually IO hub only support 2600M MAX
 230         },
 231
 232         /* The 2nd element in the array merely terminates the list */
 233         {
 234                 HT_LIST_TERMINAL,
 235         }
 236 };
 237 #else /* HYPERTRANSPORT_V31_SUPPORT == 0 */
 238 CONST CPU_TO_CPU_PCB_LIMITS ROMDATA s8226_cpu2cpu_limit_list[2] =
 239 {
 240         {
 241                 /* On the reference platform, these settings apply to all coherent links */
 242                 HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
 243
 244                 /* Set incoming and outgoing links to 16 bit widths, and 1GHz frequencies */
 245                 HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_HT1_ONLY,
 246         },
 247
 248         /* The 2nd element in the array merely terminates the list */
 249         {
 250                 HT_LIST_TERMINAL,
 251         }
 252 };
 253
 254 CONST IO_PCB_LIMITS ROMDATA s8226_io_limit_list[2] =
 255 {
 256         {
 257                 /* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */
 258                 HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY,
 259
 260                 /* Set incoming and outgoing links to 16 bit widths, and 1GHz frequencies */
 261                 HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_HT1_ONLY,
 262         },
 263
 264         /* The 2nd element in the array merely terminates the list */
 265         {
 266                 HT_LIST_TERMINAL
 267         }
 268 };
 269 #endif /* HYPERTRANSPORT_V31_SUPPORT == 0 */
 270
 271 /**
 272  * HyperTransport links will typically require an equalization at high frequencies.
 273  * This is called deemphasis.
 274  *
 275  * Deemphasis is specified as levels, for example, -3 db.
 276  * There are two levels for each link, its receiver deemphasis level and its DCV level,
 277  * which is based on the far side transmitter's deemphasis.
 278  * For each link, different levels may be required at each link frequency.
 279  *
 280  * Coherent connections between processors should have an entry for the port on each processor.
 281  * There should be one entry for the host root port of each non-coherent chain.
 282  *
 283  * AGESA initialization code does not set deemphasis on IO Devices.
 284  * A default is provided for internal links of MCM processors, and
 285  * those links will generally not need deemphasis structures.
 286  */
 287 CONST CPU_HT_DEEMPHASIS_LEVEL ROMDATA s8226_deemphasis_list[] =
 288 {
 289         /* Socket, Link, LowFreq, HighFreq, Receiver Deemphasis, Dcv Deemphasis */
 290
 291         /* Non-coherent link deemphasis. */
 292         {0, 2, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
 293         {0, 2, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5},
 294         {0, 2, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5},
 295         {0, 2, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7},
 296         {0, 2, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7},
 297         {0, 2, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9},
 298
 299         {1, 2, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
 300         {1, 2, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5},
 301         {1, 2, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5},
 302         {1, 2, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7},
 303         {1, 2, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7},
 304         {1, 2, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9},
 305
 306         {2, 0, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
 307         {2, 0, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5},
 308         {2, 0, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5},
 309         {2, 0, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7},
 310         {2, 0, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7},
 311         {2, 0, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9},
 312
 313         {3, 0, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
 314         {3, 0, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus5},
 315         {3, 0, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus5},
 316         {3, 0, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus7},
 317         {3, 0, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus7},
 318         {3, 0, HT_FREQUENCY_2600M, HT_FREQUENCY_2600M, DeemphasisLevelMinus11pre8, DcvLevelMinus9},
 319
 320         /* Coherent link deemphasis. */
 321         {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT3_FREQUENCY_MIN, HT_FREQUENCY_1600M, DeemphasisLevelNone, DcvLevelNone},
 322         {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_1800M, HT_FREQUENCY_1800M, DeemphasisLevelMinus3, DcvLevelMinus3},
 323         {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2000M, HT_FREQUENCY_2000M, DeemphasisLevelMinus6, DcvLevelMinus6},
 324         {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2200M, HT_FREQUENCY_2200M, DeemphasisLevelMinus6, DcvLevelMinus6},
 325         {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2400M, HT_FREQUENCY_2400M, DeemphasisLevelMinus8, DcvLevelMinus8},
 326         {HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2600M, HT_FREQUENCY_MAX, DeemphasisLevelMinus11pre8, DcvLevelMinus11},
 327
 328         /* End of the list */
 329         {
 330                 HT_LIST_TERMINAL
 331         }
 332 };
 333
 334 /**
 335  * For systems using socket infrastructure that permits strapping the SBI
 336  * address for each socket, this should be used to provide a socket ID value.
 337  * This is referred to as the hardware method for socket naming, and is the
 338  * preferred solution.
 339  */
 340 /*
 341  * I do NOT know howto config socket id in simnow,
 342  * so use this software way to make HT works in simnow,
 343  * real hardware do not need this Socket Map.
 344  *
 345  * A physical socket map for a 4 G34 Sockets MCM processors topology,
 346  * reference the mainboard schemantic in detail.
 347  *
 348  */
 349 CONST SYSTEM_PHYSICAL_SOCKET_MAP ROMDATA s8226_socket_map[] =
 350 {
 351 #define HT_SOCKET0      0
 352 #define HT_SOCKET1      1
 353 #define HT_SOCKET2      2
 354 #define HT_SOCKET3      3
 355
 356 /**
 357  * 0-3 are sublink 0, 4-7 are sublink 1
 358  */
 359 #define HT_LINK0A       0
 360 #define HT_LINK1A       1
 361 #define HT_LINK2A       2
 362 #define HT_LINK3A       3
 363 #define HT_LINK0B       4
 364 #define HT_LINK1B       5
 365 #define HT_LINK2B       6
 366 #define HT_LINK3B       7
 367
 368         /* Source Socket, Link, Target Socket */
 369 /*      {HT_SOCKET0, HT_LINK0A, HT_SOCKET1},
 370         {HT_SOCKET0, HT_LINK0B, HT_SOCKET3},
 371         {HT_SOCKET0, HT_LINK1A, HT_SOCKET1},
 372         {HT_SOCKET0, HT_LINK1B, HT_SOCKET3},
 373         {HT_SOCKET0, HT_LINK3A, HT_SOCKET2},
 374         {HT_SOCKET0, HT_LINK3B, HT_SOCKET2},
 375
 376         {HT_SOCKET1, HT_LINK0A, HT_SOCKET2},
 377         {HT_SOCKET1, HT_LINK0B, HT_SOCKET3},
 378         {HT_SOCKET1, HT_LINK1A, HT_SOCKET0},
 379         {HT_SOCKET1, HT_LINK1B, HT_SOCKET2},
 380         {HT_SOCKET1, HT_LINK3A, HT_SOCKET0},
 381         {HT_SOCKET1, HT_LINK3B, HT_SOCKET3},
 382
 383         {HT_SOCKET2, HT_LINK0A, HT_SOCKET3},
 384         {HT_SOCKET2, HT_LINK0B, HT_SOCKET0},
 385         {HT_SOCKET2, HT_LINK1A, HT_SOCKET3},
 386         {HT_SOCKET2, HT_LINK1B, HT_SOCKET1},
 387         {HT_SOCKET2, HT_LINK3A, HT_SOCKET1},
 388         {HT_SOCKET2, HT_LINK3B, HT_SOCKET0},
 389
 390         {HT_SOCKET3, HT_LINK0A, HT_SOCKET2},
 391         {HT_SOCKET3, HT_LINK0B, HT_SOCKET1},
 392         {HT_SOCKET3, HT_LINK1A, HT_SOCKET1},
 393         {HT_SOCKET3, HT_LINK1B, HT_SOCKET0},
 394         {HT_SOCKET3, HT_LINK3A, HT_SOCKET0},
 395         {HT_SOCKET3, HT_LINK3B, HT_SOCKET2}, */
 396 };
 397
 398 CONST AP_MTRR_SETTINGS ROMDATA s8226_ap_mtrr_list[] =
 399 {
 400         {AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E},
 401         {AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E},
 402         {AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000},
 403         {AMD_AP_MTRR_FIX4k_C0000,  0x0000000000000000},
 404         {AMD_AP_MTRR_FIX4k_C8000,  0x0000000000000000},
 405         {AMD_AP_MTRR_FIX4k_D0000,  0x0000000000000000},
 406         {AMD_AP_MTRR_FIX4k_D8000,  0x0000000000000000},
 407         {AMD_AP_MTRR_FIX4k_E0000,  0x1818181818181818},
 408         {AMD_AP_MTRR_FIX4k_E8000,  0x1818181818181818},
 409         {AMD_AP_MTRR_FIX4k_F0000,  0x1818181818181818},
 410         {AMD_AP_MTRR_FIX4k_F8000,  0x1818181818181818},
 411         {CPU_LIST_TERMINAL}
 412 };
 413
 414 #define BLDCFG_BUID_SWAP_LIST                   &s8226_manual_swaplist
 415 #define BLDCFG_HTFABRIC_LIMITS_LIST             &s8226_cpu2cpu_limit_list
 416 #define BLDCFG_HTCHAIN_LIMITS_LIST              &s8226_io_limit_list
 417 #define BLDCFG_PLATFORM_DEEMPHASIS_LIST         &s8226_deemphasis_list
 418 #define BLDCFG_AP_MTRR_SETTINGS_LIST            &s8226_ap_mtrr_list
 419 //#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP     &s8226_socket_map
 420
 421
 422 /*  Process the options...
 423  * This file include MUST occur AFTER the user option selection settings
 424  */
 425
 426 #include "SanMarinoInstall.h"