src/mainboard/lippert/toucan-af/OemCustomize.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include "AGESA.h"
  17 #include "amdlib.h"
  18 #include "heapManager.h"
  19 #include <PlatformMemoryConfiguration.h>
  20 #include "PlatformGnbPcieComplex.h"
  21
  22 #include <string.h>
  23 #include <northbridge/amd/agesa/state_machine.h>
  24
  25
  26 /*---------------------------------------------------------------------------------------*/
  27 /**
  28  *      OemCustomizeInitEarly
  29  *
  30  *      Description:
  31  *      This stub function will call the host environment through the binary block
  32  *      interface (call-out port) to provide a user hook opportunity
  33  *
  34  *      Parameters:
  35  *      @param[in]              *InitEarly
  36  *
  37  *      @retval          VOID
  38  *
  39  **/
  40 /*---------------------------------------------------------------------------------------*/
  41
  42 void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
  43 {
  44         AGESA_STATUS             Status;
  45         VOID                             *BrazosPcieComplexListPtr;
  46         VOID                             *BrazosPciePortPtr;
  47         VOID                             *BrazosPcieDdiPtr;
  48
  49         ALLOCATE_HEAP_PARAMS AllocHeapParams;
  50
  51 PCIe_PORT_DESCRIPTOR PortList [] = {
  52                 // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
  53                 {
  54                         0,
  55                         PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
  56                         PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 0)
  57                 },
  58                 // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
  59                 {
  60                         0,
  61                         PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5),
  62                         PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 0)
  63                 },
  64                 // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
  65                 {
  66                         0,
  67                         PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
  68                         PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 0)
  69                 },
  70                 // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
  71                 {
  72                         0,
  73                         PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
  74                         PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0)
  75                 },
  76                 // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
  77                 {
  78                         DESCRIPTOR_TERMINATE_LIST,
  79                         PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
  80                         PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
  81                 }
  82 };
  83
  84 PCIe_DDI_DESCRIPTOR DdiList [] = {
  85                 // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
  86                 {
  87                         0,
  88                         PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
  89                         //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
  90                         {ConnectorTypeAutoDetect, Aux1, Hdp1}
  91                 },
  92                 // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
  93                 {
  94                         DESCRIPTOR_TERMINATE_LIST,
  95                         PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
  96                         //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
  97                         {ConnectorTypeAutoDetect, Aux2, Hdp2}
  98                 }
  99 };
 100
 101 PCIe_COMPLEX_DESCRIPTOR Brazos = {
 102                 DESCRIPTOR_TERMINATE_LIST,
 103                 0,
 104                 &PortList[0],
 105                 &DdiList[0]
 106 };
 107
 108         // GNB PCIe topology Porting
 109
 110         //
 111         // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
 112         //
 113         AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList);
 114
 115         AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
 116         AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
 117         Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
 118         ASSERT(Status == AGESA_SUCCESS);
 119
 120         BrazosPcieComplexListPtr        =       (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
 121
 122         AllocHeapParams.BufferPtr += sizeof(Brazos);
 123         BrazosPciePortPtr                =      (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
 124
 125         AllocHeapParams.BufferPtr += sizeof(PortList);
 126         BrazosPcieDdiPtr                        =       (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
 127
 128         memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos));
 129         memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList));
 130         memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList));
 131
 132
 133         ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList =    (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
 134         ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList       =       (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
 135
 136         InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
 137         InitEarly->GnbConfig.PsppPolicy         = 0;
 138 }
 139
 140 /*----------------------------------------------------------------------------------------
 141  *                                              CUSTOMER OVERIDES MEMORY TABLE
 142  *----------------------------------------------------------------------------------------
 143  */
 144
 145 /*
 146  *      Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
 147  *      (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
 148  *      is populated, AGESA will base its settings on the data from the table. Otherwise, it will
 149  *      use its default conservative settings.
 150  */
 151 static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
 152         HW_RXEN_SEED (ANY_SOCKET, ANY_CHANNEL, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B),
 153         NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
 154         NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
 155         PSO_END
 156 };
 157
 158 void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
 159 {
 160         InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
 161 }