src/mainboard/jetway/nf81-t56n-lf/buildOpts.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 /**
  17  * @file
  18  *
  19  * AMD User options selection for a Brazos platform solution system
  20  *
  21  * This file is placed in the user's platform directory and contains the
  22  * build option selections desired for that platform.
  23  *
  24  * For Information about this file, see @ref platforminstall.
  25  *
  26  */
  27
  28 #include <stdlib.h>
  29
  30 #include <vendorcode/amd/agesa/f14/AGESA.h>
  31
  32 /* Include the files that instantiate the configuration definitions. */
  33 #include <vendorcode/amd/agesa/f14/Include/AdvancedApi.h>
  34 #include <vendorcode/amd/agesa/f14/Proc/CPU/cpuFamilyTranslation.h>
  35 #include <vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuFeatures.h>
  36 #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
  37 /* AGESA nonesense: the next two headers depend on heapManager.h */
  38 #include <vendorcode/amd/agesa/f14/Proc/Common/CreateStruct.h>
  39 #include <vendorcode/amd/agesa/f14/Proc/CPU/cpuEarlyInit.h>
  40 /* These tables are optional and may be used to adjust memory timing settings */
  41 #include <vendorcode/amd/agesa/f14/Proc/Mem/mm.h>
  42 #include <vendorcode/amd/agesa/f14/Proc/Mem/mn.h>
  43
  44
  45 /* Select the CPU family. */
  46 #define INSTALL_FAMILY_10_SUPPORT FALSE
  47 #define INSTALL_FAMILY_12_SUPPORT FALSE
  48 #define INSTALL_FAMILY_14_SUPPORT TRUE
  49 #define INSTALL_FAMILY_15_SUPPORT FALSE
  50
  51 /* Select the CPU socket type. */
  52 #define INSTALL_G34_SOCKET_SUPPORT      FALSE
  53 #define INSTALL_C32_SOCKET_SUPPORT      FALSE
  54 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE
  55 #define INSTALL_S1G4_SOCKET_SUPPORT FALSE
  56 #define INSTALL_ASB2_SOCKET_SUPPORT FALSE
  57 #define INSTALL_FS1_SOCKET_SUPPORT      FALSE
  58 #define INSTALL_FM1_SOCKET_SUPPORT      FALSE
  59 #define INSTALL_FP1_SOCKET_SUPPORT      FALSE
  60 #define INSTALL_FT1_SOCKET_SUPPORT      TRUE
  61 #define INSTALL_AM3_SOCKET_SUPPORT      FALSE
  62
  63 /**
  64  * AGESA optional capabilities selection.
  65  * Uncomment and mark FALSE those features you wish to include in the build.
  66  * Comment out or mark TRUE those features you want to REMOVE from the build.
  67  */
  68
  69 #define BLDOPT_REMOVE_FAMILY_10_SUPPORT                 TRUE
  70 #define BLDOPT_REMOVE_FAMILY_12_SUPPORT                 TRUE
  71 #define BLDOPT_REMOVE_FAMILY_14_SUPPORT                 FALSE
  72 #define BLDOPT_REMOVE_FAMILY_15_SUPPORT                 TRUE
  73
  74 #define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT                TRUE
  75 #define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT               TRUE
  76 #define BLDOPT_REMOVE_C32_SOCKET_SUPPORT                TRUE
  77 #define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT                TRUE
  78 #define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT                TRUE
  79 #define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT                TRUE
  80 #define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT                FALSE
  81 #define BLDOPT_REMOVE_G34_SOCKET_SUPPORT                TRUE
  82 #define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT               TRUE
  83 #define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT               TRUE
  84
  85 #define BLDOPT_REMOVE_UDIMMS_SUPPORT                    FALSE
  86 #define BLDOPT_REMOVE_RDIMMS_SUPPORT                    TRUE
  87 #define BLDOPT_REMOVE_LRDIMMS_SUPPORT                   FALSE
  88 #define BLDOPT_REMOVE_ECC_SUPPORT                               FALSE
  89 //#define BLDOPT_REMOVE_DCT_INTERLEAVE                  TRUE
  90 #define BLDOPT_REMOVE_BANK_INTERLEAVE                   FALSE
  91 #define BLDOPT_REMOVE_NODE_INTERLEAVE                   TRUE
  92 #define BLDOPT_REMOVE_PARALLEL_TRAINING                 FALSE
  93 #define BLDOPT_REMOVE_DQS_TRAINING                              FALSE
  94 #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT              TRUE
  95 #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT               TRUE
  96                 #define BLDOPT_REMOVE_ACPI_PSTATES                              FALSE
  97                 #define BLDCFG_REMOVE_ACPI_PSTATES_PPC                  FALSE
  98                 #define BLDCFG_REMOVE_ACPI_PSTATES_PCT                  FALSE
  99                 #define BLDCFG_REMOVE_ACPI_PSTATES_PSD                  FALSE
 100                 #define BLDCFG_REMOVE_ACPI_PSTATES_PSS                  FALSE
 101                 #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS                 FALSE
 102                 #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT             FALSE
 103 #define BLDOPT_REMOVE_SRAT                                              FALSE
 104 #define BLDOPT_REMOVE_SLIT                                              FALSE
 105 #define BLDOPT_REMOVE_WHEA                                              FALSE
 106 #define BLDOPT_REMOVE_DMI                                               TRUE
 107 #define BLDOPT_REMOVE_HT_ASSIST                                 TRUE
 108 #define BLDOPT_REMOVE_ATM_MODE                                  TRUE
 109 //#define BLDOPT_REMOVE_MSG_BASED_C1E                   TRUE
 110 //#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT     TRUE
 111 #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT               FALSE
 112 //#define BLDOPT_REMOVE_C6_STATE                                TRUE
 113 #define BLDOPT_REMOVE_GFX_RECOVERY                              TRUE
 114 #define BLDOPT_REMOVE_EARLY_SAMPLES                             TRUE
 115
 116
 117 #define BLDCFG_PCI_MMIO_BASE                                    CONFIG_MMCONF_BASE_ADDRESS
 118 #define BLDCFG_PCI_MMIO_SIZE                                    CONFIG_MMCONF_BUS_NUMBER
 119
 120 #define BLDCFG_VRM_CURRENT_LIMIT                                24000
 121 //#define BLDCFG_VRM_NB_CURRENT_LIMIT                   0
 122 #define BLDCFG_VRM_LOW_POWER_THRESHOLD                  24000
 123 #define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD               1
 124 #define BLDCFG_VRM_SLEW_RATE                                    5000
 125 //#define BLDCFG_VRM_NB_SLEW_RATE                               5000
 126 //#define BLDCFG_VRM_ADDITIONAL_DELAY                   0
 127 //#define BLDCFG_VRM_NB_ADDITIONAL_DELAY                0
 128 #define BLDCFG_VRM_HIGH_SPEED_ENABLE                    TRUE
 129 //#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE               FALSE
 130 #define BLDCFG_VRM_INRUSH_CURRENT_LIMIT                 6000
 131 //#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT    0
 132
 133 //#define BLDCFG_PROCESSOR_SCOPE_NAME0                  'C'
 134 //#define BLDCFG_PROCESSOR_SCOPE_NAME1                  '0'
 135 //#define BLDCFG_PROCESSOR_SCOPE_IN_SB                  FALSE
 136 #define BLDCFG_PLAT_NUM_IO_APICS                                3
 137 //#define BLDCFG_PLATFORM_C1E_MODE                              C1eModeDisabled
 138 //#define BLDCFG_PLATFORM_C1E_OPDATA                    0
 139 //#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1              0
 140 //#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2              0
 141 #define BLDCFG_PLATFORM_CSTATE_MODE                             CStateModeC6
 142 #define BLDCFG_PLATFORM_CSTATE_OPDATA                   0x840
 143 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS  0x840
 144 //#define BLDCFG_PLATFORM_CPB_MODE                              CpbModeAuto
 145 #define BLDCFG_CORE_LEVELING_MODE                               CORE_LEVEL_LOWEST
 146 #define BLDCFG_AP_MTRR_SETTINGS_LIST                    &OntarioApMtrrSettingsList
 147 #define BLDCFG_AMD_PLATFORM_TYPE                                AMD_PLATFORM_MOBILE
 148 //#define BLDCFG_STARTING_BUSNUM                                0
 149 //#define BLDCFG_MAXIMUM_BUSNUM                                 0xf8
 150 //#define BLDCFG_ALLOCATED_BUSNUMS                              0x20
 151 //#define BLDCFG_PLATFORM_DEEMPHASIS_LIST               0
 152 //#define BLDCFG_BUID_SWAP_LIST                                 0
 153 //#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST    0
 154 //#define BLDCFG_HTFABRIC_LIMITS_LIST                   0
 155 //#define BLDCFG_HTCHAIN_LIMITS_LIST                    0
 156 //#define BLDCFG_BUS_NUMBERS_LIST                               0
 157 //#define BLDCFG_IGNORE_LINK_LIST                               0
 158 //#define BLDCFG_LINK_SKIP_REGANG_LIST                  0
 159 //#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST             0
 160 //#define BLDCFG_USE_HT_ASSIST                                  TRUE
 161 //#define BLDCFG_USE_ATM_MODE                                   TRUE
 162 //#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE             Nfcm
 163 #define BLDCFG_S3_LATE_RESTORE                                  TRUE
 164 //#define BLDCFG_USE_32_BYTE_REFRESH                    FALSE
 165 //#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE
 166 //#define BLDCFG_PLATFORM_POWER_POLICY_MODE             Performance
 167 //#define BLDCFG_SET_HTCRC_SYNC_FLOOD                   FALSE
 168 //#define BLDCFG_USE_UNIT_ID_CLUMPING                   FALSE
 169 //#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP             0
 170 #define BLDCFG_CFG_GNB_HD_AUDIO                                 FALSE
 171 //#define BLDCFG_CFG_ABM_SUPPORT                                FALSE
 172 //#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE               0
 173 //#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL             0
 174 //#define BLDCFG_MEM_INIT_PSTATE                                0
 175 //#define BLDCFG_AMD_PSTATE_CAP_VALUE                   0
 176 #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT               DDR1333_FREQUENCY
 177 #define BLDCFG_MEMORY_MODE_UNGANGED                             TRUE
 178 //#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE               TRUE
 179 //#define BLDCFG_MEMORY_QUADRANK_TYPE                   QUADRANK_UNBUFFERED
 180 #define BLDCFG_MEMORY_SODIMM_CAPABLE                    TRUE
 181 #define BLDCFG_MEMORY_LRDIMM_CAPABLE                    FALSE
 182 #define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING  TRUE
 183 #define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING  FALSE
 184 #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING              FALSE
 185 #define BLDCFG_MEMORY_POWER_DOWN                                TRUE
 186 #define BLDCFG_POWER_DOWN_MODE                                  POWER_DOWN_BY_CHIP_SELECT
 187 //#define BLDCFG_ONLINE_SPARE                                   FALSE
 188 //#define BLDCFG_MEMORY_PARITY_ENABLE                   FALSE
 189 #define BLDCFG_BANK_SWIZZLE                                             TRUE
 190 #define BLDCFG_TIMING_MODE_SELECT                               TIMING_MODE_AUTO
 191 #define BLDCFG_MEMORY_CLOCK_SELECT                              DDR1333_FREQUENCY
 192 #define BLDCFG_DQS_TRAINING_CONTROL                             TRUE
 193 #define BLDCFG_IGNORE_SPD_CHECKSUM                              FALSE
 194 #define BLDCFG_USE_BURST_MODE                                   FALSE
 195 #define BLDCFG_MEMORY_ALL_CLOCKS_ON                             FALSE
 196 //#define BLDCFG_ENABLE_ECC_FEATURE                             TRUE
 197 //#define BLDCFG_ECC_REDIRECTION                                FALSE
 198 //#define BLDCFG_SCRUB_DRAM_RATE                                0
 199 //#define BLDCFG_SCRUB_L2_RATE                                  0
 200 //#define BLDCFG_SCRUB_L3_RATE                                  0
 201 //#define BLDCFG_SCRUB_IC_RATE                                  0
 202 //#define BLDCFG_SCRUB_DC_RATE                                  0
 203 //#define BLDCFG_ECC_SYNC_FLOOD                                 0
 204 //#define BLDCFG_ECC_SYMBOL_SIZE                                0
 205 //#define BLDCFG_1GB_ALIGN                                              FALSE
 206 #define BLDCFG_UMA_ALLOCATION_MODE                              UMA_AUTO
 207 #define BLDCFG_UMA_ALLOCATION_SIZE                              0
 208 #define BLDCFG_UMA_ABOVE4G_SUPPORT                              FALSE
 209 #define BLDCFG_UMA_ALIGNMENT                                    NO_UMA_ALIGNED
 210 #define BLDCFG_HEAP_DRAM_ADDRESS                                0xB0000
 211 #define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS  0xD0000000
 212
 213 /**
 214  * AGESA configuration values selection.
 215  * Uncomment and specify the value for the configuration options
 216  * needed by the system.
 217  */
 218
 219 /* The fixed MTRR values to be set after memory initialization. */
 220 const AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
 221 {
 222         { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
 223         { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
 224         { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
 225         { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
 226         { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
 227         { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
 228         { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
 229         { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
 230         { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
 231         { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
 232         { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
 233         { CPU_LIST_TERMINAL }
 234 };
 235
 236 /**
 237  * @brief Define the RELEASE VERSION string
 238  *
 239  * The Release Version string should identify the next planned release.
 240  * When a branch is made in preparation for a release, the release manager
 241  * should change/confirm that the branch version of this file contains the
 242  * string matching the desired version for the release. The trunk version of
 243  * the file should always contain a trailing 'X'. This will make sure that a
 244  * development build from trunk will not be confused for a released version.
 245  * The release manager will need to remove the trailing 'X' and update the
 246  * version string as appropriate for the release. The trunk copy of this file
 247  * should also be updated/incremented for the next expected version, + trailing 'X'
 248  */
 249
 250 /*
 251  * This is the delivery package title, "BrazosPI"
 252  * This string MUST be exactly 8 characters long
 253  */
 254 #define AGESA_PACKAGE_STRING    {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
 255
 256 /* This is the release version number of the AGESA component
 257  * This string MUST be exactly 12 characters long
 258  */
 259 #define AGESA_VERSION_STRING    {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '}
 260
 261 /* MEMORY_BUS_SPEED */
 262 #define DDR400_FREQUENCY                                200 /**< DDR 400 */
 263 #define DDR533_FREQUENCY                                266 /**< DDR 533 */
 264 #define DDR667_FREQUENCY                                333 /**< DDR 667 */
 265 #define DDR800_FREQUENCY                                400 /**< DDR 800 */
 266 #define DDR1066_FREQUENCY                               533 /**< DDR 1066 */
 267 #define DDR1333_FREQUENCY                               667 /**< DDR 1333 */
 268 #define DDR1600_FREQUENCY                               800 /**< DDR 1600 */
 269 #define DDR1866_FREQUENCY                               933 /**< DDR 1866 */
 270 #define UNSUPPORTED_DDR_FREQUENCY               934 /**< Max limit of DDR frequency */
 271
 272 /* QUANDRANK_TYPE*/
 273 #define QUADRANK_REGISTERED                             0 /**< Quadrank registered DIMM */
 274 #define QUADRANK_UNBUFFERED                             1 /**< Quadrank unbuffered DIMM */
 275
 276 /* USER_MEMORY_TIMING_MODE */
 277 #define TIMING_MODE_AUTO                                0 /**< Use best rate possible */
 278 #define TIMING_MODE_LIMITED                             1 /**< Set user top limit */
 279 #define TIMING_MODE_SPECIFIC                    2 /**< Set user specified speed */
 280
 281 /* POWER_DOWN_MODE */
 282 #define POWER_DOWN_BY_CHANNEL                   0 /**< Channel power down mode */
 283 #define POWER_DOWN_BY_CHIP_SELECT               1 /**< Chip select power down mode */
 284
 285 /**
 286  * The following definitions specify the default values for various parameters
 287  * in which there are no clearly defined defaults to be used in the common
 288  * file. The values below are based on product and BKDG content.
 289  */
 290 #define DFLT_SCRUB_DRAM_RATE                    (0)
 291 #define DFLT_SCRUB_L2_RATE                              (0)
 292 #define DFLT_SCRUB_L3_RATE                              (0)
 293 #define DFLT_SCRUB_IC_RATE                              (0)
 294 #define DFLT_SCRUB_DC_RATE                              (0)
 295 #define DFLT_MEMORY_QUADRANK_TYPE               QUADRANK_UNBUFFERED
 296 #define DFLT_VRM_SLEW_RATE                              (5000)
 297
 298 /* AGESA nonsense: this header depends on the definitions above */
 299 /* Instantiate all solution relevant data. */
 300 #include <vendorcode/amd/agesa/f14/Include/PlatformInstall.h>