src/mainboard/hp/abm/OemCustomize.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2012 Advanced Micro Devices, Inc.
   5  * Copyright (C) 2014 Sage Electronic Engineering, LLC
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include "AGESA.h"
  18 #include "amdlib.h"
  19 #include "heapManager.h"
  20 #include <PlatformMemoryConfiguration.h>
  21
  22 #include <northbridge/amd/agesa/state_machine.h>
  23
  24
  25 static const PCIe_PORT_DESCRIPTOR PortList [] = {
  26         {
  27                 0,
  28                 PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 3, 3),
  29                 PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5,
  30                                 HotplugDisabled,
  31                                 PcieGenMaxSupported,
  32                                 PcieGenMaxSupported,
  33                                 AspmDisabled, 0x01, 0)
  34         },
  35         /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */
  36         {
  37                 0,
  38                 PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 2),
  39                 PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4,
  40                                 HotplugDisabled,
  41                                 PcieGenMaxSupported,
  42                                 PcieGenMaxSupported,
  43                                 AspmDisabled, 0x02, 0)
  44         },
  45         /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
  46         {
  47                 0,
  48                 PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1),
  49                 PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3,
  50                                 HotplugDisabled,
  51                                 PcieGenMaxSupported,
  52                                 PcieGenMaxSupported,
  53                                 AspmDisabled, 0x03, 0)
  54         },
  55         /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
  56         {
  57                 0,
  58                 PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0),
  59                 PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2,
  60                                 HotplugDisabled,
  61                                 PcieGenMaxSupported,
  62                                 PcieGenMaxSupported,
  63                                 AspmDisabled, 0x04, 0)
  64         },
  65         /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
  66         {
  67                 DESCRIPTOR_TERMINATE_LIST,
  68                 PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7),
  69                 PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1,
  70                                 HotplugDisabled,
  71                                 PcieGenMaxSupported,
  72                                 PcieGenMaxSupported,
  73                                 AspmDisabled, 0x05, 0)
  74         }
  75 };
  76
  77 static const PCIe_DDI_DESCRIPTOR DdiList [] = {
  78         /* DP0 to HDMI0/DP */
  79         {
  80                 0,
  81                 PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
  82                 PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux1, Hdp1)
  83         },
  84         /* DP1 to FCH */
  85         {
  86                 DESCRIPTOR_TERMINATE_LIST,
  87                 PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
  88                 PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2)
  89         },
  90 };
  91
  92 static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
  93         .Flags        = DESCRIPTOR_TERMINATE_LIST,
  94         .SocketId     = 0,
  95         .PciePortList = PortList,
  96         .DdiLinkList  = DdiList
  97 };
  98
  99 void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
 100 {
 101         FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface;
 102         FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
 103         FchReset->Xhci1Enable = FALSE;
 104 }
 105
 106 /*---------------------------------------------------------------------------------------*/
 107 /**
 108  *  OemCustomizeInitEarly
 109  *
 110  *  Description:
 111  *    This is the stub function will call the host environment through the binary block
 112  *    interface (call-out port) to provide a user hook opportunity
 113  *
 114  *  Parameters:
 115  *    @param[in]      **PeiServices
 116  *    @param[in]      *InitEarly
 117  *
 118  *    @retval         VOID
 119  *
 120  **/
 121 /*---------------------------------------------------------------------------------------*/
 122
 123 void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
 124 {
 125         AGESA_STATUS            Status;
 126         PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr;
 127
 128         ALLOCATE_HEAP_PARAMS AllocHeapParams;
 129
 130         /* GNB PCIe topology Porting */
 131
 132         /*  */
 133         /* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */
 134         /*  */
 135         AllocHeapParams.RequestedBufferSize = sizeof(PcieComplex);
 136
 137         AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
 138         AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
 139         Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
 140         ASSERT(Status == AGESA_SUCCESS);
 141
 142         PcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
 143         LibAmdMemCopy  (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader);
 144         InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr;
 145 }
 146
 147 /*----------------------------------------------------------------------------------------
 148  *                        CUSTOMER OVERIDES MEMORY TABLE
 149  *----------------------------------------------------------------------------------------
 150  */
 151
 152 /*
 153  *  Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
 154  *  (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
 155  *  is populated, AGESA will base its settings on the data from the table. Otherwise, it will
 156  *  use its default conservative settings.
 157  */
 158 static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
 159         #define SEED_A 0x12
 160         HW_RXEN_SEED(
 161                 ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
 162                 SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
 163                 SEED_A),
 164
 165   NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, ONE_DIMM),
 166   NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, ONE_DIMM),
 167   MOTHER_BOARD_LAYERS (LAYERS_6),
 168
 169   MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
 170   CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */
 171   ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08),
 172   CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00),
 173
 174   PSO_END
 175 };
 176
 177 void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
 178 {
 179         InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
 180 }
 181
 182 void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid)
 183 {
 184         /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
 185         InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
 186 }