src/mainboard/gizmosphere/gizmo/OemCustomize.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Advanced Micro Devices, Inc.
   5  * Copyright (C) 2013 Sage Electronic Engineering, LLC
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include "AGESA.h"
  18 #include "amdlib.h"
  19 #include "heapManager.h"
  20 #include <PlatformMemoryConfiguration.h>
  21 #include "PlatformGnbPcieComplex.h"
  22 #include "Filecode.h"
  23
  24 #include <string.h>
  25 #include <northbridge/amd/agesa/state_machine.h>
  26
  27 /*---------------------------------------------------------------------------------------*/
  28 /**
  29  *      OemCustomizeInitEarly
  30  *
  31  *      Description:
  32  *      This stub function will call the host environment through the binary block
  33  *      interface (call-out port) to provide a user hook opportunity
  34  *
  35  *      Parameters:
  36  *      @param[in]              *InitEarly
  37  *
  38  *      @retval          VOID
  39  *
  40  **/
  41 /*---------------------------------------------------------------------------------------*/
  42
  43 void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
  44 {
  45         AGESA_STATUS             Status;
  46         VOID                             *BrazosPcieComplexListPtr;
  47         VOID                             *BrazosPciePortPtr;
  48         VOID                             *BrazosPcieDdiPtr;
  49
  50         ALLOCATE_HEAP_PARAMS AllocHeapParams;
  51
  52 PCIe_PORT_DESCRIPTOR PortList [] = {
  53                 // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
  54                 {
  55                         0,
  56                         PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
  57                         PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 4)
  58                 },
  59                 // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
  60                 {
  61                         0,
  62                         PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5),
  63                         PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 5)
  64                 },
  65                 // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
  66                 {
  67                         0,
  68                         PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
  69                         PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 6)
  70                 },
  71                 // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
  72                 {
  73                         0,
  74                         PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
  75                         PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 7)
  76                 },
  77                 // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
  78                 {
  79                         DESCRIPTOR_TERMINATE_LIST,
  80                         PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
  81                         PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
  82                 }
  83 };
  84
  85 PCIe_DDI_DESCRIPTOR DdiList [] = {
  86                 // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
  87                 {
  88                         0,
  89                         PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
  90                         //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
  91                         {ConnectorTypeDP, Aux1, Hdp1}
  92                 },
  93                 // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
  94                 {
  95                         DESCRIPTOR_TERMINATE_LIST,
  96                         PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
  97                         //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
  98                         {ConnectorTypeDP, Aux2, Hdp2}
  99                 }
 100 };
 101
 102 PCIe_COMPLEX_DESCRIPTOR Brazos = {
 103                 DESCRIPTOR_TERMINATE_LIST,
 104                 0,
 105                 &PortList[0],
 106                 &DdiList[0]
 107 };
 108
 109         // GNB PCIe topology Porting
 110
 111         //
 112         // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
 113         //
 114         AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList);
 115
 116         AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
 117         AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
 118         Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
 119         ASSERT(Status == AGESA_SUCCESS);
 120
 121         BrazosPcieComplexListPtr        =       (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
 122
 123         AllocHeapParams.BufferPtr += sizeof(Brazos);
 124         BrazosPciePortPtr                =      (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
 125
 126         AllocHeapParams.BufferPtr += sizeof(PortList);
 127         BrazosPcieDdiPtr                        =       (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
 128
 129         memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos));
 130         memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList));
 131         memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList));
 132
 133
 134         ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList =    (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
 135         ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList       =       (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
 136
 137         InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
 138         InitEarly->GnbConfig.PsppPolicy         = 0;
 139 }
 140
 141 /*----------------------------------------------------------------------------------------
 142  *                                              CUSTOMER OVERIDES MEMORY TABLE
 143  *----------------------------------------------------------------------------------------
 144  */
 145
 146 /*
 147  *      Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
 148  *      (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
 149  *      is populated, AGESA will base its settings on the data from the table. Otherwise, it will
 150  *      use its default conservative settings.
 151  */
 152 static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
 153
 154         NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, TWO_DIMM),
 155         NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, ONE_DIMM),
 156
 157         // Gizmos soldered down memory uses memory CLK0 and CLK1 on CS0
 158         MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
 159
 160         // Gizmos soldered down memory requires different seeds
 161 #define WLSEED 0x08
 162 #define RXSEED 0x40
 163         WRITE_LEVELING_SEED(ANY_SOCKET, ANY_CHANNEL, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED, WLSEED),
 164         HW_RXEN_SEED( ANY_SOCKET, ANY_CHANNEL, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED, RXSEED),
 165
 166         PSO_END
 167 };
 168
 169 void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
 170 {
 171         InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
 172 }