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AGESA boards: Clean up Ids.h and Filecode.h includes
[coreboot.git] / src / mainboard / elmex / pcm205400 / buildOpts.c
bloba90ee799053546701b57e79615762e3c3df0aa32
1 /*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2011 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 /**
17 * @file
18 *
19 * AMD User options selection for a Brazos platform solution system
20 *
21 * This file is placed in the user's platform directory and contains the
22 * build option selections desired for that platform.
23 *
24 * For Information about this file, see @ref platforminstall.
25 *
26 */
27
28 #include <stdlib.h>
29
30
31 /* Select the cpu family. */
32 #define INSTALL_FAMILY_10_SUPPORT FALSE
33 #define INSTALL_FAMILY_12_SUPPORT FALSE
34 #define INSTALL_FAMILY_14_SUPPORT TRUE
35 #define INSTALL_FAMILY_15_SUPPORT FALSE
36
37 /* Select the cpu socket type. */
38 #define INSTALL_G34_SOCKET_SUPPORT FALSE
39 #define INSTALL_C32_SOCKET_SUPPORT FALSE
40 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE
41 #define INSTALL_S1G4_SOCKET_SUPPORT FALSE
42 #define INSTALL_ASB2_SOCKET_SUPPORT FALSE
43 #define INSTALL_FS1_SOCKET_SUPPORT FALSE
44 #define INSTALL_FM1_SOCKET_SUPPORT FALSE
45 #define INSTALL_FP1_SOCKET_SUPPORT FALSE
46 #define INSTALL_FT1_SOCKET_SUPPORT TRUE
47 #define INSTALL_AM3_SOCKET_SUPPORT FALSE
48
49 /*
50 * Agesa optional capabilities selection.
51 * Uncomment and mark FALSE those features you wish to include in the build.
52 * Comment out or mark TRUE those features you want to REMOVE from the build.
53 */
54
55 #define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE
56 #define BLDOPT_REMOVE_FAMILY_12_SUPPORT TRUE
57 #define BLDOPT_REMOVE_FAMILY_14_SUPPORT FALSE
58 #define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE
59
60 #define BLDOPT_REMOVE_AM3_SOCKET_SUPPORT TRUE
61 #define BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT TRUE
62 #define BLDOPT_REMOVE_C32_SOCKET_SUPPORT TRUE
63 #define BLDOPT_REMOVE_FM1_SOCKET_SUPPORT TRUE
64 #define BLDOPT_REMOVE_FP1_SOCKET_SUPPORT TRUE
65 #define BLDOPT_REMOVE_FS1_SOCKET_SUPPORT TRUE
66 #define BLDOPT_REMOVE_FT1_SOCKET_SUPPORT FALSE
67 #define BLDOPT_REMOVE_G34_SOCKET_SUPPORT TRUE
68 #define BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT TRUE
69 #define BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT TRUE
70
71 #define BLDOPT_REMOVE_UDIMMS_SUPPORT FALSE
72 #define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
73 #define BLDOPT_REMOVE_LRDIMMS_SUPPORT FALSE
74 #define BLDOPT_REMOVE_ECC_SUPPORT FALSE
75 //#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
76 #define BLDOPT_REMOVE_BANK_INTERLEAVE FALSE
77 #define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
78 #define BLDOPT_REMOVE_PARALLEL_TRAINING FALSE
79 #define BLDOPT_REMOVE_DQS_TRAINING FALSE
80 #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
81 #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
82 #define BLDOPT_REMOVE_ACPI_PSTATES FALSE
83 #define BLDCFG_REMOVE_ACPI_PSTATES_PPC FALSE
84 #define BLDCFG_REMOVE_ACPI_PSTATES_PCT FALSE
85 #define BLDCFG_REMOVE_ACPI_PSTATES_PSD FALSE
86 #define BLDCFG_REMOVE_ACPI_PSTATES_PSS FALSE
87 #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS FALSE
88 #define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT FALSE
89 #define BLDOPT_REMOVE_SRAT FALSE
90 #define BLDOPT_REMOVE_SLIT FALSE
91 #define BLDOPT_REMOVE_WHEA FALSE
92 #define BLDOPT_REMOVE_DMI TRUE
93 #define BLDOPT_REMOVE_HT_ASSIST TRUE
94 #define BLDOPT_REMOVE_ATM_MODE TRUE
95 //#define BLDOPT_REMOVE_MSG_BASED_C1E TRUE
96 //#define BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT TRUE
97 #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT FALSE
98 //#define BLDOPT_REMOVE_C6_STATE TRUE
99 #define BLDOPT_REMOVE_GFX_RECOVERY TRUE
100 #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE
101
102
103 #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
104 #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
105
106 #define BLDCFG_VRM_CURRENT_LIMIT 24000
107 //#define BLDCFG_VRM_NB_CURRENT_LIMIT 0
108 #define BLDCFG_VRM_LOW_POWER_THRESHOLD 24000
109 #define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1
110 #define BLDCFG_VRM_SLEW_RATE 5000
111 //#define BLDCFG_VRM_NB_SLEW_RATE 5000
112 //#define BLDCFG_VRM_ADDITIONAL_DELAY 0
113 //#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0
114 #define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
115 //#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE FALSE
116 #define BLDCFG_VRM_INRUSH_CURRENT_LIMIT 6000
117 //#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0
118
119 //#define BLDCFG_PROCESSOR_SCOPE_NAME0 'C'
120 //#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
121 //#define BLDCFG_PROCESSOR_SCOPE_IN_SB FALSE
122 #define BLDCFG_PLAT_NUM_IO_APICS 3
123 //#define BLDCFG_PLATFORM_C1E_MODE C1eModeDisabled
124 //#define BLDCFG_PLATFORM_C1E_OPDATA 0
125 //#define BLDCFG_PLATFORM_C1E_MODE_OPDATA1 0
126 //#define BLDCFG_PLATFORM_C1E_MODE_OPDATA2 0
127 #define BLDCFG_PLATFORM_CSTATE_MODE CStateModeC6
128 #define BLDCFG_PLATFORM_CSTATE_OPDATA 0x840
129 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x840
130 //#define BLDCFG_PLATFORM_CPB_MODE CpbModeAuto
131 #define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
132 #define BLDCFG_AP_MTRR_SETTINGS_LIST &OntarioApMtrrSettingsList
133 #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
134 //#define BLDCFG_STARTING_BUSNUM 0
135 //#define BLDCFG_MAXIMUM_BUSNUM 0xf8
136 //#define BLDCFG_ALLOCATED_BUSNUMS 0x20
137 //#define BLDCFG_PLATFORM_DEEMPHASIS_LIST 0
138 //#define BLDCFG_BUID_SWAP_LIST 0
139 //#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST 0
140 //#define BLDCFG_HTFABRIC_LIMITS_LIST 0
141 //#define BLDCFG_HTCHAIN_LIMITS_LIST 0
142 //#define BLDCFG_BUS_NUMBERS_LIST 0
143 //#define BLDCFG_IGNORE_LINK_LIST 0
144 //#define BLDCFG_LINK_SKIP_REGANG_LIST 0
145 //#define BLDCFG_ADDITIONAL_TOPOLOGIES_LIST 0
146 //#define BLDCFG_USE_HT_ASSIST TRUE
147 //#define BLDCFG_USE_ATM_MODE TRUE
148 //#define BLDCFG_PLATFORM_CONTROL_FLOW_MODE Nfcm
149 #define BLDCFG_S3_LATE_RESTORE TRUE
150 //#define BLDCFG_USE_32_BYTE_REFRESH FALSE
151 //#define BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY FALSE
152 //#define BLDCFG_PLATFORM_POWER_POLICY_MODE Performance
153 //#define BLDCFG_SET_HTCRC_SYNC_FLOOD FALSE
154 //#define BLDCFG_USE_UNIT_ID_CLUMPING FALSE
155 //#define BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP 0
156 #define BLDCFG_CFG_GNB_HD_AUDIO FALSE
157 //#define BLDCFG_CFG_ABM_SUPPORT FALSE
158 //#define BLDCFG_CFG_DYNAMIC_REFRESH_RATE 0
159 //#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 0
160 //#define BLDCFG_MEM_INIT_PSTATE 0
161 //#define BLDCFG_AMD_PSTATE_CAP_VALUE 0
162 #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY
163 #define BLDCFG_MEMORY_MODE_UNGANGED TRUE
164 //#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
165 //#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
166 #define BLDCFG_MEMORY_SODIMM_CAPABLE TRUE
167 #define BLDCFG_MEMORY_LRDIMM_CAPABLE FALSE
168 #define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
169 #define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
170 #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE
171 #define BLDCFG_MEMORY_POWER_DOWN TRUE
172 #define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
173 //#define BLDCFG_ONLINE_SPARE FALSE
174 //#define BLDCFG_MEMORY_PARITY_ENABLE FALSE
175 #define BLDCFG_BANK_SWIZZLE TRUE
176 #define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
177 #define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY
178 #define BLDCFG_DQS_TRAINING_CONTROL TRUE
179 #define BLDCFG_IGNORE_SPD_CHECKSUM FALSE
180 #define BLDCFG_USE_BURST_MODE FALSE
181 #define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
182 //#define BLDCFG_ENABLE_ECC_FEATURE TRUE
183 //#define BLDCFG_ECC_REDIRECTION FALSE
184 //#define BLDCFG_SCRUB_DRAM_RATE 0
185 //#define BLDCFG_SCRUB_L2_RATE 0
186 //#define BLDCFG_SCRUB_L3_RATE 0
187 //#define BLDCFG_SCRUB_IC_RATE 0
188 //#define BLDCFG_SCRUB_DC_RATE 0
189 //#define BLDCFG_ECC_SYNC_FLOOD 0
190 //#define BLDCFG_ECC_SYMBOL_SIZE 0
191 //#define BLDCFG_1GB_ALIGN FALSE
192 #define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO
193 #define BLDCFG_UMA_ALLOCATION_SIZE 0
194 #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE
195 #define BLDCFG_UMA_ALIGNMENT NO_UMA_ALIGNED
196 #define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000
197 #define BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000
198
199 /*
200 * Agesa configuration values selection.
201 * Uncomment and specify the value for the configuration options
202 * needed by the system.
203 */
204 #include "AGESA.h"
205
206 /* The fixed MTRR values to be set after memory initialization. */
207 CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] =
208 {
209 { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
210 { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
211 { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
212 { AMD_AP_MTRR_FIX4k_C0000, 0x1E1E1E1E1E1E1E1Eull },
213 { AMD_AP_MTRR_FIX4k_C8000, 0x1E1E1E1E1E1E1E1Eull },
214 { AMD_AP_MTRR_FIX4k_D0000, 0x1E1E1E1E1E1E1E1Eull },
215 { AMD_AP_MTRR_FIX4k_D8000, 0x1E1E1E1E1E1E1E1Eull },
216 { AMD_AP_MTRR_FIX4k_E0000, 0x1E1E1E1E1E1E1E1Eull },
217 { AMD_AP_MTRR_FIX4k_E8000, 0x1E1E1E1E1E1E1E1Eull },
218 { AMD_AP_MTRR_FIX4k_F0000, 0x1E1E1E1E1E1E1E1Eull },
219 { AMD_AP_MTRR_FIX4k_F8000, 0x1E1E1E1E1E1E1E1Eull },
220 { CPU_LIST_TERMINAL }
221 };
222
223 /* Include the files that instantiate the configuration definitions. */
224
225 #include "cpuRegisters.h"
226 #include "cpuFamRegisters.h"
227 #include "cpuFamilyTranslation.h"
228 #include "AdvancedApi.h"
229 #include "heapManager.h"
230 #include "CreateStruct.h"
231 #include "cpuFeatures.h"
232 #include "Table.h"
233 #include "cpuEarlyInit.h"
234 #include "cpuLateInit.h"
235 #include "GnbInterface.h"
236
237 /*****************************************************************************
238 * Define the RELEASE VERSION string
239 *
240 * The Release Version string should identify the next planned release.
241 * When a branch is made in preparation for a release, the release manager
242 * should change/confirm that the branch version of this file contains the
243 * string matching the desired version for the release. The trunk version of
244 * the file should always contain a trailing 'X'. This will make sure that a
245 * development build from trunk will not be confused for a released version.
246 * The release manager will need to remove the trailing 'X' and update the
247 * version string as appropriate for the release. The trunk copy of this file
248 * should also be updated/incremented for the next expected version, + trailing 'X'
249 ****************************************************************************/
250 // This is the delivery package title, "BrazosPI"
251 // This string MUST be exactly 8 characters long
252 #define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
253
254 // This is the release version number of the AGESA component
255 // This string MUST be exactly 12 characters long
256 #define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '3', ' ', ' ', ' ', ' '}
257
258 /* MEMORY_BUS_SPEED */
259 #define DDR400_FREQUENCY 200 ///< DDR 400
260 #define DDR533_FREQUENCY 266 ///< DDR 533
261 #define DDR667_FREQUENCY 333 ///< DDR 667
262 #define DDR800_FREQUENCY 400 ///< DDR 800
263 #define DDR1066_FREQUENCY 533 ///< DDR 1066
264 #define DDR1333_FREQUENCY 667 ///< DDR 1333
265 #define DDR1600_FREQUENCY 800 ///< DDR 1600
266 #define DDR1866_FREQUENCY 933 ///< DDR 1866
267 #define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency
268
269 /* QUANDRANK_TYPE*/
270 #define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
271 #define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
272
273 /* USER_MEMORY_TIMING_MODE */
274 #define TIMING_MODE_AUTO 0 ///< Use best rate possible
275 #define TIMING_MODE_LIMITED 1 ///< Set user top limit
276 #define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
277
278 /* POWER_DOWN_MODE */
279 #define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
280 #define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
281
282 // The following definitions specify the default values for various parameters in which there are
283 // no clearly defined defaults to be used in the common file. The values below are based on product
284 // and BKDG content, please consult the AGESA Memory team for consultation.
285 #define DFLT_SCRUB_DRAM_RATE (0)
286 #define DFLT_SCRUB_L2_RATE (0)
287 #define DFLT_SCRUB_L3_RATE (0)
288 #define DFLT_SCRUB_IC_RATE (0)
289 #define DFLT_SCRUB_DC_RATE (0)
290 #define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
291 #define DFLT_VRM_SLEW_RATE (5000)
292
293 // Instantiate all solution relevant data.
294 #include "PlatformInstall.h"
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