src/mainboard/amd/torpedo/buildOpts.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 /**
  17  * @file
  18  *
  19  * AMD User options selection for a Sabine/Lynx platform solution system
  20  *
  21  * This file is placed in the user's platform directory and contains the
  22  * build option selections desired for that platform.
  23  *
  24  * For Information about this file, see @ref platforminstall.
  25  *
  26  */
  27
  28 #include <stdlib.h>
  29 #include "AGESA.h"
  30
  31
  32 /*  Select the CPU family.  */
  33 #define INSTALL_FAMILY_10_SUPPORT FALSE
  34 #define INSTALL_FAMILY_12_SUPPORT TRUE
  35 #define INSTALL_FAMILY_14_SUPPORT FALSE
  36 #define INSTALL_FAMILY_15_SUPPORT FALSE
  37
  38 /*  Select the CPU socket type.  */
  39 #define INSTALL_G34_SOCKET_SUPPORT  FALSE
  40 #define INSTALL_C32_SOCKET_SUPPORT  FALSE
  41 #define INSTALL_S1G3_SOCKET_SUPPORT FALSE
  42 #define INSTALL_S1G4_SOCKET_SUPPORT FALSE
  43 #define INSTALL_ASB2_SOCKET_SUPPORT FALSE
  44 #define INSTALL_FS1_SOCKET_SUPPORT  TRUE
  45 #define INSTALL_FM1_SOCKET_SUPPORT  FALSE
  46 #define INSTALL_FP1_SOCKET_SUPPORT  TRUE
  47 #define INSTALL_FT1_SOCKET_SUPPORT  FALSE
  48 #define INSTALL_AM3_SOCKET_SUPPORT  FALSE
  49
  50 /*
  51  * Agesa optional capabilities selection.
  52  * Uncomment and mark FALSE those features you wish to include in the build.
  53  * Comment out or mark TRUE those features you want to REMOVE from the build.
  54  */
  55
  56 #define BLDOPT_REMOVE_UDIMMS_SUPPORT           FALSE
  57 #define BLDOPT_REMOVE_RDIMMS_SUPPORT           FALSE
  58 #define BLDOPT_REMOVE_ECC_SUPPORT              FALSE
  59 #define BLDOPT_REMOVE_BANK_INTERLEAVE          FALSE
  60 #define BLDOPT_REMOVE_DCT_INTERLEAVE           FALSE
  61 #define BLDOPT_REMOVE_NODE_INTERLEAVE          TRUE
  62 #define BLDOPT_REMOVE_PARALLEL_TRAINING        TRUE
  63 #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT     TRUE
  64 #define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT      FALSE
  65 #define BLDOPT_REMOVE_DDR2_SUPPORT             TRUE
  66 #define BLDOPT_REMOVE_DDR3_SUPPORT             FALSE
  67 #define BLDOPT_REMOVE_MULTISOCKET_SUPPORT      TRUE
  68 #define BLDOPT_REMOVE_ACPI_PSTATES             FALSE
  69 #define BLDOPT_REMOVE_SRAT                     TRUE
  70 #define BLDOPT_REMOVE_SLIT                     TRUE
  71 #define BLDOPT_REMOVE_WHEA                     TRUE
  72 #define BLDOPT_REMOVE_DMI                      FALSE
  73 #define BLDOPT_REMOVE_EARLY_SAMPLES            TRUE
  74 #define BLDCFG_REMOVE_ACPI_PSTATES_PPC         FALSE
  75 #define BLDCFG_REMOVE_ACPI_PSTATES_PCT         FALSE
  76 #define BLDCFG_REMOVE_ACPI_PSTATES_PSD         FALSE
  77 #define BLDCFG_REMOVE_ACPI_PSTATES_PSS         FALSE
  78 #define BLDCFG_REMOVE_ACPI_PSTATES_XPSS        FALSE
  79
  80 //For revision C single-link processors
  81 #define BLDCFG_SUPPORT_ACPI_PSTATES_PSD_INDPX  TRUE
  82
  83
  84 /*****************************************************************************
  85  *   Define the RELEASE VERSION string
  86  *
  87  * The Release Version string should identify the next planned release.
  88  * When a branch is made in preparation for a release, the release manager
  89  * should change/confirm that the branch version of this file contains the
  90  * string matching the desired version for the release. The trunk version of
  91  * the file should always contain a trailing 'X'. This will make sure that a
  92  * development build from trunk will not be confused for a released version.
  93  * The release manager will need to remove the trailing 'X' and update the
  94  * version string as appropriate for the release. The trunk copy of this file
  95  * should also be updated/incremented for the next expected version, + trailing 'X'
  96  ****************************************************************************/
  97                         // This is the delivery package title, "LlanoPI "
  98                         // This string MUST be exactly 8 characters long
  99 #define AGESA_PACKAGE_STRING  {'L', 'l', 'a', 'n', 'o', 'P', 'I', ' '}
 100
 101                         // This is the release version number of the AGESA component
 102                         // This string MUST be exactly 12 characters long
 103 #define AGESA_VERSION_STRING  {'V', '1', '.', '1', '.', '0', '.', '0', ' ', ' ', ' ', ' '}
 104
 105 /* The following definitions specify the default values for various parameters
 106  * in which there are no clearly defined defaults to be used in the common file.
 107  * The values below are based on product and BKDG content, please consult the
 108  * AGESA Memory team for consultation.
 109  */
 110 #define DFLT_SCRUB_DRAM_RATE            (0)
 111 #define DFLT_SCRUB_L2_RATE              (0)
 112 #define DFLT_SCRUB_L3_RATE              (0)
 113 #define DFLT_SCRUB_IC_RATE              (0)
 114 #define DFLT_SCRUB_DC_RATE              (0)
 115 #define DFLT_MEMORY_QUADRANK_TYPE       QUADRANK_UNBUFFERED
 116 #define DFLT_VRM_SLEW_RATE              (5000)
 117
 118 /* Build configuration values here.
 119  */
 120 #define BLDCFG_VRM_CURRENT_LIMIT                 65000  //240000 //120000
 121 #define BLDCFG_VRM_LOW_POWER_THRESHOLD           15000  // 0
 122 #define BLDCFG_VRM_INRUSH_CURRENT_LIMIT          0
 123 #define BLDCFG_PLAT_NUM_IO_APICS                 3
 124 #define BLDCFG_CORE_LEVELING_MODE                CORE_LEVEL_LOWEST
 125 #define BLDCFG_MEM_INIT_PSTATE                   0
 126
 127 #define BLDCFG_AMD_PLATFORM_TYPE                  AMD_PLATFORM_MOBILE
 128
 129 #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT         DDR1866_FREQUENCY //DDR1066_FREQUENCY
 130 #define BLDCFG_MEMORY_MODE_UNGANGED               TRUE
 131 #define BLDCFG_MEMORY_QUAD_RANK_CAPABLE           TRUE
 132 #define BLDCFG_MEMORY_QUADRANK_TYPE               QUADRANK_REGISTERED
 133 #define BLDCFG_MEMORY_RDIMM_CAPABLE               TRUE
 134 #define BLDCFG_MEMORY_UDIMM_CAPABLE               TRUE
 135 #define BLDCFG_MEMORY_SODIMM_CAPABLE              TRUE
 136 #define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING    TRUE
 137 #define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING    FALSE
 138 #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING        TRUE
 139 #define BLDCFG_MEMORY_POWER_DOWN                  TRUE
 140 #define BLDCFG_POWER_DOWN_MODE                    POWER_DOWN_BY_CHIP_SELECT
 141 #define BLDCFG_ONLINE_SPARE                       FALSE
 142 #define BLDCFG_MEMORY_PARITY_ENABLE               FALSE
 143 #define BLDCFG_BANK_SWIZZLE                       TRUE
 144 #define BLDCFG_TIMING_MODE_SELECT                 TIMING_MODE_AUTO
 145 #define BLDCFG_MEMORY_CLOCK_SELECT                DDR800_FREQUENCY
 146 #define BLDCFG_DQS_TRAINING_CONTROL               TRUE
 147 #define BLDCFG_IGNORE_SPD_CHECKSUM                FALSE
 148 #define BLDCFG_USE_BURST_MODE                     FALSE
 149 #define BLDCFG_MEMORY_ALL_CLOCKS_ON               FALSE
 150 #define BLDCFG_ENABLE_ECC_FEATURE                 TRUE
 151 #define BLDCFG_ECC_REDIRECTION                    FALSE
 152 #define BLDCFG_SCRUB_DRAM_RATE                    0
 153 #define BLDCFG_SCRUB_L2_RATE                      0
 154 #define BLDCFG_SCRUB_L3_RATE                      0
 155 #define BLDCFG_SCRUB_IC_RATE                      0
 156 #define BLDCFG_SCRUB_DC_RATE                      0
 157 #define BLDCFG_ECC_SYNC_FLOOD                     FALSE
 158 #define BLDCFG_ECC_SYMBOL_SIZE                    4
 159 #define BLDCFG_HEAP_DRAM_ADDRESS                  0xB0000
 160 #define BLDCFG_1GB_ALIGN                          FALSE
 161 #define BLDCFG_VRM_HIGH_SPEED_ENABLE              TRUE
 162 //#define BLDCFG_PROCESSOR_SCOPE_NAME0              'C'
 163 //#define BLDCFG_PROCESSOR_SCOPE_NAME1              '0'
 164
 165 //enable HW C1E
 166 #define BLDCFG_PLATFORM_C1E_MODE     0 //C1eModeHardware
 167 //#define BLDCFG_PLATFORM_C1E_OPDATA              0x415
 168 #define BLDCFG_PLATFORM_CSTATE_MODE     CStateModeC6 //0 //CStateModeC6
 169 //#define BLDCFG_PLATFORM_CSTATE_OPDATA   0x840         //Specifies a free block of 8 consecutive I/O ports to be used to place the CPU into C6
 170 #define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS   0x840         //Specifies a free block of 8 consecutive I/O ports to be used to place the CPU into C6
 171
 172
 173 //#define BLDCFG_VRM_NB_CURRENT_LIMIT               0  // Not currently used on Llano/Ontario
 174 #define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD         1  // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L.  Default is Zero.
 175 //#define BLDCFG_VRM_NB_SLEW_RATE                   5000 // Used in calculating the VSRampSlamTime per BKDG.  Defaults to 5000, same as core VRM.  Cannot be zero.
 176 //#define BLDCFG_VRM_NB_ADDITIONAL_DELAY            0  // Not currently used on Llano/Ontario
 177 //#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE           0  // Not currently used on Llano/Ontario
 178 //#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT        0  // Not currently used on Llano/Ontario
 179
 180 #define BLDCFG_UMA_ABOVE4G_SUPPORT              TRUE
 181 #define BLDCFG_STEREO_3D_PINOUT                 TRUE
 182
 183 /*  Process the options...
 184  * This file include MUST occur AFTER the user option selection settings
 185  */
 186 CONST AP_MTRR_SETTINGS ROMDATA LlanoApMtrrSettingsList[] =
 187 {
 188         { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1Eull },
 189         { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1Eull },
 190         { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000ull },
 191         { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000ull },
 192         { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000ull },
 193         { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000ull },
 194         { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000ull },
 195         { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818ull },
 196         { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818ull },
 197         { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818ull },
 198         { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818ull },
 199         { CPU_LIST_TERMINAL }
 200 };
 201
 202 #define BLDCFG_AP_MTRR_SETTINGS_LIST &LlanoApMtrrSettingsList
 203 //#define OPTION_NB_LCLK_DPM_INIT FALSE
 204 //#define OPTION_POWER_GATE       FALSE
 205 //#define OPTION_PCIE_POWER_GATE  FALSE
 206 //#define OPTION_ALIB             FALSE
 207 //#define OPTION_PCIe_MID_INIT  FALSE
 208 //#define OPTION_NB_MID_INIT    FALSE
 209
 210 #include "cpuRegisters.h"
 211 #include "cpuFamRegisters.h"
 212 #include "cpuFamilyTranslation.h"
 213 #include "AdvancedApi.h"
 214 #include "heapManager.h"
 215 #include "CreateStruct.h"
 216 #include "cpuFeatures.h"
 217 #include "Table.h"
 218 #include "cpuEarlyInit.h"
 219 #include "cpuLateInit.h"
 220 #include "GnbInterface.h"
 221 #include "PlatformInstall.h"