src/mainboard/amd/torpedo/BiosCallOuts.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include "AGESA.h"
  17 #include "amdlib.h"
  18 #include <northbridge/amd/agesa/BiosCallOuts.h>
  19 #include "Hudson-2.h"
  20 #include <stdlib.h>
  21 #include <southbridge/amd/cimx/sb700/gpio_oem.h>
  22
  23 static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr);
  24 static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr);
  25
  26 const BIOS_CALLOUT_STRUCT BiosCallouts[] =
  27 {
  28         {AGESA_DO_RESET,                        agesa_Reset },
  29         {AGESA_READ_SPD,                        agesa_ReadSpd },
  30         {AGESA_READ_SPD_RECOVERY,               agesa_NoopUnsupported },
  31         {AGESA_RUNFUNC_ONAP,                    agesa_RunFuncOnAp },
  32         {AGESA_GNB_PCIE_SLOT_RESET,             board_GnbPcieSlotReset },
  33         {AGESA_GET_IDS_INIT_DATA,               agesa_EmptyIdsInitData },
  34         {AGESA_HOOKBEFORE_DRAM_INIT,            board_BeforeDramInit },
  35         {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY,   agesa_NoopSuccess },
  36         {AGESA_HOOKBEFORE_DQS_TRAINING,         agesa_NoopSuccess },
  37         {AGESA_HOOKBEFORE_EXIT_SELF_REF,        agesa_NoopSuccess },
  38 };
  39 const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
  40
  41 /*  Call the host environment interface to provide a user hook opportunity. */
  42 static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr)
  43 {
  44         AGESA_STATUS      Status;
  45         UINTN             FcnData;
  46         MEM_DATA_STRUCT   *MemData;
  47         UINT32            AcpiMmioAddr;
  48         UINT32            GpioMmioAddr;
  49         UINT8             Data8;
  50         UINT16            Data16;
  51
  52         FcnData = Data;
  53         MemData = ConfigPtr;
  54
  55         Status  = AGESA_SUCCESS;
  56         /* Get SB MMIO Base (AcpiMmioAddr) */
  57         WriteIo8 (0xCD6, 0x27);
  58         Data8   = ReadIo8(0xCD7);
  59         Data16  = Data8 << 8;
  60         WriteIo8 (0xCD6, 0x26);
  61         Data8   = ReadIo8(0xCD7);
  62         Data16  |= Data8;
  63         AcpiMmioAddr = (UINT32)Data16 << 16;
  64         GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
  65
  66         switch(MemData->ParameterListPtr->DDR3Voltage){
  67                 case VOLT1_35:
  68                         Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
  69                         Data8 &= ~(UINT8)BIT6;
  70                         Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
  71                         Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
  72                         Data8 |= (UINT8)BIT6;
  73                         Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
  74                         break;
  75                 case VOLT1_25:
  76                         Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
  77                         Data8 &= ~(UINT8)BIT6;
  78                         Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
  79                         Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179);
  80                         Data8 &= ~(UINT8)BIT6;
  81                         Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8);
  82                         break;
  83                 case VOLT1_5:
  84                 default:
  85                         Data8 =  Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178);
  86                         Data8 |= (UINT8)BIT6;
  87                         Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8);
  88         }
  89         return Status;
  90 }
  91
  92 /* PCIE slot reset control */
  93 static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr)
  94 {
  95         AGESA_STATUS Status;
  96         UINTN                 FcnData;
  97         PCIe_SLOT_RESET_INFO  *ResetInfo;
  98
  99         UINT32  GpioMmioAddr;
 100         UINT32  AcpiMmioAddr;
 101         UINT8   Data8;
 102         UINT16  Data16;
 103
 104         FcnData   = Data;
 105         ResetInfo = ConfigPtr;
 106         // Get SB MMIO Base (AcpiMmioAddr)
 107         WriteIo8(0xCD6, 0x27);
 108         Data8 = ReadIo8(0xCD7);
 109         Data16 = Data8 << 8;
 110         WriteIo8(0xCD6, 0x26);
 111         Data8 = ReadIo8(0xCD7);
 112         Data16 |= Data8;
 113         AcpiMmioAddr = (UINT32)Data16 << 16;
 114         Status = AGESA_UNSUPPORTED;
 115         GpioMmioAddr = AcpiMmioAddr + GPIO_BASE;
 116
 117         if (ResetInfo->ResetControl == DeassertSlotReset) {
 118                 if (ResetInfo->ResetId & (BIT2+BIT3)) {    //de-assert
 119                         // [GPIO] GPIO45: PE_GPIO1 MXM_POWER_ENABLE, SET HIGH
 120                         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG45);
 121                         if (Data8 & BIT7) {
 122                                 Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG28);
 123                                 while (!(Data8 & BIT7)) {
 124                                         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG28);
 125                                 }
 126                                 // GPIO44: PE_GPIO0 MXM Reset
 127                                 Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG44);
 128                                 Data8 |= BIT6 ;
 129                                 Write64Mem8 (GpioMmioAddr+SB_GPIO_REG44, Data8);
 130                                 Status = AGESA_SUCCESS;
 131                         }
 132                 } else {
 133                         Status = AGESA_UNSUPPORTED;
 134                 }
 135                 // Travis
 136                 Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG24);
 137                 Data8 |= BIT6;
 138                 Write64Mem8 (GpioMmioAddr+SB_GPIO_REG24, Data8);
 139                 //DE-Assert ALL PCIE RESET
 140                 // APU GPP0 (Dev 4)
 141                 Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
 142                 Data8 |= BIT6;
 143                 Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);
 144                 // APU GPP1 (Dev 5)
 145                 Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG01);
 146                 Data8 |= BIT6;
 147                 Write64Mem8 (GpioMmioAddr+SB_GPIO_REG01, Data8);
 148                 // APU GPP2 (Dev 6)
 149                 Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG00);
 150                 Data8 |= BIT6;
 151                 Write64Mem8 (GpioMmioAddr+SB_GPIO_REG00, Data8);
 152                 // APU GPP3 (Dev 7)
 153                 Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG27);
 154                 Data8 |= BIT6;
 155                 Write64Mem8 (GpioMmioAddr+SB_GPIO_REG27, Data8);
 156         } else {
 157                 if (ResetInfo->ResetId & (BIT2+BIT3)) {  //Pcie Slot Reset is supported
 158                         // GPIO44: PE_GPIO0 MXM Reset
 159                         Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG44);
 160                         Data8 &= ~(UINT8)BIT6;
 161                         Write64Mem8 (GpioMmioAddr+SB_GPIO_REG44, Data8);
 162                         Status = AGESA_SUCCESS;
 163                 }
 164                 // Travis
 165                 Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG24);
 166                 Data8 &= ~(UINT8)BIT6;
 167                 Write64Mem8 (GpioMmioAddr+SB_GPIO_REG24, Data8);
 168                 //Assert ALL PCIE RESET
 169                 // APU GPP0 (Dev 4)
 170                 Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG25);
 171                 Data8 &= ~(UINT8)BIT6;
 172                 Write64Mem8 (GpioMmioAddr+SB_GPIO_REG25, Data8);
 173                 // APU GPP1 (Dev 5)
 174                 Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG01);
 175                 Data8 &= ~(UINT8)BIT6;
 176                 Write64Mem8 (GpioMmioAddr+SB_GPIO_REG01, Data8);
 177                 // APU GPP2 (Dev 6)
 178                 Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG00);
 179                 Data8 &= ~(UINT8)BIT6;
 180                 Write64Mem8 (GpioMmioAddr+SB_GPIO_REG00, Data8);
 181                 // APU GPP3 (Dev 7)
 182                 Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG27);
 183                 Data8 &= ~(UINT8)BIT6;
 184                 Write64Mem8 (GpioMmioAddr+SB_GPIO_REG27, Data8);
 185         }
 186         return  Status;
 187 }