src/mainboard/amd/persimmon/OemCustomize.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include "PlatformGnbPcieComplex.h"
  17
  18 #include <string.h>
  19 #include <northbridge/amd/agesa/state_machine.h>
  20 #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h>
  21 #include <PlatformMemoryConfiguration.h>
  22
  23
  24 /**
  25  *      OemCustomizeInitEarly
  26  *
  27  *      Description:
  28  *      This stub function will call the host environment through the binary block
  29  *      interface (call-out port) to provide a user hook opportunity
  30  *
  31  *      Parameters:
  32  *      @param[in]              *InitEarly
  33  *
  34  *      @retval          VOID
  35  *
  36  **/
  37
  38 void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
  39 {
  40         AGESA_STATUS             Status;
  41         VOID                             *BrazosPcieComplexListPtr;
  42         VOID                             *BrazosPciePortPtr;
  43         VOID                             *BrazosPcieDdiPtr;
  44
  45         ALLOCATE_HEAP_PARAMS AllocHeapParams;
  46
  47 PCIe_PORT_DESCRIPTOR PortList [] = {
  48                 // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
  49                 {
  50                         0,
  51                         PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
  52                         PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 46)
  53                 },
  54                 // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
  55                 {
  56                         0,
  57                         PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5),
  58                         PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 46)
  59                 },
  60                 // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
  61                 {
  62                         0,
  63                         PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
  64                         PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 46)
  65                 },
  66                 // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
  67                 {
  68                         0,
  69                         PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
  70                         PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0)
  71                 },
  72                 // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
  73                 {
  74                         DESCRIPTOR_TERMINATE_LIST,
  75                         PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
  76                         PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0)
  77                 }
  78 };
  79
  80 PCIe_DDI_DESCRIPTOR DdiList [] = {
  81                 // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...)
  82                 {
  83                         0,
  84                         PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
  85                         //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
  86                         {ConnectorTypeLvds, Aux1, Hdp1}
  87                 },
  88                 // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...)
  89                 {
  90                         DESCRIPTOR_TERMINATE_LIST,
  91                         PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
  92                         //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
  93                         {ConnectorTypeDP, Aux2, Hdp2}
  94                 }
  95 };
  96
  97 PCIe_COMPLEX_DESCRIPTOR Brazos = {
  98                 DESCRIPTOR_TERMINATE_LIST,
  99                 0,
 100                 &PortList[0],
 101                 &DdiList[0]
 102 };
 103
 104         // GNB PCIe topology Porting
 105
 106         //
 107         // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
 108         //
 109         AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList);
 110
 111         AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
 112         AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
 113         Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
 114         ASSERT(Status == AGESA_SUCCESS);
 115
 116         BrazosPcieComplexListPtr        =       (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
 117
 118         AllocHeapParams.BufferPtr += sizeof(Brazos);
 119         BrazosPciePortPtr                =      (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
 120
 121         AllocHeapParams.BufferPtr += sizeof(PortList);
 122         BrazosPcieDdiPtr                        =       (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
 123
 124         memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos));
 125         memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList));
 126         memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList));
 127
 128
 129         ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList =    (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr;
 130         ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList       =       (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr;
 131
 132         InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
 133         InitEarly->GnbConfig.PsppPolicy         = 0;
 134 }
 135
 136 /*----------------------------------------------------------------------------------------
 137  *                                              CUSTOMER OVERIDES MEMORY TABLE
 138  *----------------------------------------------------------------------------------------
 139  */
 140
 141 /*
 142  *      Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
 143  *      (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
 144  *      is populated, AGESA will base its settings on the data from the table. Otherwise, it will
 145  *      use its default conservative settings.
 146  */
 147 static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
 148         NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
 149         NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
 150         PSO_END
 151 };
 152
 153 void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
 154 {
 155         InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
 156 }