src/mainboard/amd/lamar/OemCustomize.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2012        Advanced Micro Devices, Inc.
   5  *               2013 - 2014 Sage Electronic Engineering, LLC
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <northbridge/amd/pi/agesawrapper.h>
  18
  19
  20 static const PCIe_PORT_DESCRIPTOR PortList [] = {
  21
  22         /*
  23          * Lanes to pins to PCI device mapping can be found in section 2.12 of the
  24          * BIOS and Kernel Developer's Guide for AMD Family 15h Models 30h-3Fh
  25          */
  26
  27         {       /* PCIe x16 Connector J119, DP4/5/6, GFX[15:0], Lanes [31:16], PCI 00:02.1 */
  28                 0,
  29                 PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 31),
  30                 PCIE_PORT_DATA_INITIALIZER_V2 (
  31                                 PortEnabled,
  32                                 ChannelTypeExt6db, 0, 0,
  33                                 HotplugDisabled,
  34                                 PcieGenMaxSupported,
  35                                 PcieGenMaxSupported,
  36                                 AspmDisabled,
  37                                 175,
  38                                 0
  39                 )
  40         },
  41
  42         {       /* PCIe x4 Connector J118, GPP[3:0], Lanes [11:8], PCI 00:03.2 */
  43                 0,
  44                 PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 11),
  45                 PCIE_PORT_DATA_INITIALIZER_V2 (
  46                                 PortEnabled,
  47                                 ChannelTypeExt6db, 0, 0,
  48                                 HotplugDisabled,
  49                                 PcieGenMaxSupported,
  50                                 PcieGenMaxSupported,
  51                                 AspmDisabled,
  52                                 176,
  53                                 0
  54                 )
  55         },
  56
  57         {       /* PCIe x4 Connector J120, GPP[7:4], Lanes [15:12] */
  58                 DESCRIPTOR_TERMINATE_LIST,
  59                 PCIE_ENGINE_DATA_INITIALIZER (
  60                                 IS_ENABLED(CONFIG_ENABLE_DP3_DAUGHTER_CARD_IN_J120) ? PcieUnusedEngine : PciePortEngine,
  61                                 12, 15
  62                 ),
  63                 PCIE_PORT_DATA_INITIALIZER_V2 (
  64                                 PortEnabled,
  65                                 ChannelTypeExt6db, 0, 0,
  66                                 HotplugDisabled,
  67                                 PcieGenMaxSupported, PcieGenMaxSupported,
  68                                 AspmDisabled,
  69                                 177,
  70                                 0
  71                 )
  72         },
  73
  74 };
  75
  76 static const PCIe_DDI_DESCRIPTOR DdiList [] = {
  77         {       /* DP3 */
  78                 0,
  79                 PCIE_ENGINE_DATA_INITIALIZER (
  80                                 IS_ENABLED(CONFIG_ENABLE_DP3_DAUGHTER_CARD_IN_J120) ? PcieDdiEngine : PcieUnusedEngine,
  81                                 12, 15
  82                 ),
  83                 PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux4, Hdp4)
  84         },
  85
  86         {       /* DP2 */
  87                 0,
  88                 PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 36, 39),
  89                 PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux3, Hdp3)
  90         },
  91
  92         {       /* DP1 */
  93                 0,
  94                 PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 35),
  95                 PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
  96         },
  97
  98         {       /* DP0 */
  99                 DESCRIPTOR_TERMINATE_LIST,
 100                 PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 4, 7),
 101                 PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
 102         },
 103 };
 104
 105 static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
 106         .Flags        = DESCRIPTOR_TERMINATE_LIST,
 107         .SocketId     = 0,
 108         .PciePortList = PortList,
 109         .DdiLinkList  = DdiList
 110 };
 111
 112 /*---------------------------------------------------------------------------------------*/
 113 /**
 114  *  OemCustomizeInitEarly
 115  *
 116  *  Description:
 117  *    This stub function will call the host environment through the binary block
 118  *    interface (call-out port) to provide a user hook opportunity
 119  *
 120  *  Parameters:
 121  *    @param[in]      *InitEarly
 122  *
 123  *    @retval         VOID
 124  *
 125  **/
 126 /*---------------------------------------------------------------------------------------*/
 127 VOID
 128 OemCustomizeInitEarly (
 129         IN  OUT AMD_EARLY_PARAMS    *InitEarly
 130         )
 131 {
 132         InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
 133 }