src/mainboard/amd/bettong/OemCustomize.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2015 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <northbridge/amd/pi/agesawrapper.h>
  17 #include <PlatformMemoryConfiguration.h>
  18 #include <boardid.h>
  19
  20
  21 static const PCIe_PORT_DESCRIPTOR PortList [] = {
  22         /* Initialize Port descriptor (PCIe port, Lanes 8-15, PCI Device Number 3, ...) */
  23         {
  24                 0,
  25                 PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15),
  26                 PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 3, 1,
  27                                 HotplugDisabled,
  28                                 PcieGenMaxSupported,
  29                                 PcieGenMaxSupported,
  30                                 AspmDisabled, 0x02, 0)
  31         },
  32
  33         /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
  34         {
  35                 0,
  36                 PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
  37                 PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 5,
  38                                 HotplugDisabled,
  39                                 PcieGenMaxSupported,
  40                                 PcieGenMaxSupported,
  41                                 AspmDisabled, 0x03, 0)
  42         },
  43         /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
  44         {
  45                 0,
  46                 PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 6, 6),
  47                 PCIE_PORT_DATA_INITIALIZER_V2 (PortDisabled, ChannelTypeExt6db, 2, 4,
  48                                 HotplugDisabled,
  49                                 PcieGenMaxSupported,
  50                                 PcieGenMaxSupported,
  51                                 AspmDisabled, 0x04, 0)
  52         },
  53         /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 2, ...) */
  54         {
  55                 0,
  56                 PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 5, 5),
  57                 PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3,
  58                                 HotplugDisabled,
  59                                 PcieGenMaxSupported,
  60                                 PcieGenMaxSupported,
  61                                 AspmDisabled, 0x05, 0)
  62         },
  63         /* Initialize Port descriptor (PCIe port, Lanes 4-5, PCI Device Number 2, ...) */
  64         {
  65                 0,
  66                 PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 5),
  67                 PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2,
  68                                 HotplugDisabled,
  69                                 PcieGenMaxSupported,
  70                                 PcieGenMaxSupported,
  71                                 AspmDisabled, 0x06, 0)
  72         },
  73         /* Initialize Port descriptor (PCIe port, Lanes 0-3, PCI Device Number 2, ...) */
  74         {
  75                 DESCRIPTOR_TERMINATE_LIST, /* Descriptor flags  !!!IMPORTANT!!! Terminate last element of array */
  76                 PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
  77                 PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1,
  78                                 HotplugDisabled,
  79                                 PcieGenMaxSupported,
  80                                 PcieGenMaxSupported,
  81                                 AspmDisabled, 0x07, 0)
  82         },
  83
  84 };
  85
  86 static const PCIe_DDI_DESCRIPTOR DdiList [] = {
  87         /* DP0 */
  88         {
  89                 0,
  90                 PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19),
  91                 PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
  92         },
  93         /* DP1 */
  94         {
  95                 0, /*DESCRIPTOR_TERMINATE_LIST, */
  96                 PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 20, 23),
  97                 PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
  98         },
  99         /* DP2 */
 100         {
 101                 DESCRIPTOR_TERMINATE_LIST,
 102                 PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27),
 103                 PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux3, Hdp3)
 104         },
 105 };
 106
 107 static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
 108         .Flags        = DESCRIPTOR_TERMINATE_LIST,
 109         .SocketId     = 0,
 110         .PciePortList = PortList,
 111         .DdiLinkList  = DdiList
 112 };
 113
 114 /*---------------------------------------------------------------------------------------*/
 115 /**
 116  *  OemCustomizeInitEarly
 117  *
 118  *  Description:
 119  *    This is the stub function will call the host environment through the binary block
 120  *    interface (call-out port) to provide a user hook opportunity
 121  *
 122  *  Parameters:
 123  *    @param[in]      **PeiServices
 124  *    @param[in]      *InitEarly
 125  *
 126  *    @retval         VOID
 127  *
 128  **/
 129 /*---------------------------------------------------------------------------------------*/
 130 VOID OemCustomizeInitEarly (
 131         IN  OUT AMD_EARLY_PARAMS    *InitEarly
 132         )
 133 {
 134         InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
 135 }
 136
 137 static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = {
 138         DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),
 139         NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
 140         NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
 141         MOTHER_BOARD_LAYERS (LAYERS_6),
 142         MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
 143         CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
 144         ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff),
 145         CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
 146         PSO_END
 147 };
 148
 149 void OemPostParams(AMD_POST_PARAMS *PostParams)
 150 {
 151         if (board_id() == 'F') {
 152                 PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)DDR4PlatformMemoryConfiguration;
 153         }
 154 }