src/southbridge/amd/agesa/hudson/bootblock.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2010 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <stdint.h>
  17 #include <device/pci_ops.h>
  18
  19 /*
  20  * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
  21  *
  22  * Hardware should enable LPC ROM by pin straps. This function does not
  23  * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations.
  24  *
  25  * The HUDSON power-on default is to map 512K ROM space.
  26  *
  27  */
  28 static void hudson_enable_rom(void)
  29 {
  30         u8 reg8;
  31         pci_devfn_t dev;
  32
  33         dev = PCI_DEV(0, 0x14, 3);
  34
  35         /* Decode variable LPC ROM address ranges 1 and 2. */
  36         reg8 = pci_io_read_config8(dev, 0x48);
  37         reg8 |= (1 << 3) | (1 << 4);
  38         pci_io_write_config8(dev, 0x48, reg8);
  39
  40         /* LPC ROM address range 1: */
  41         /* Enable LPC ROM range mirroring start at 0x000e(0000). */
  42         pci_io_write_config16(dev, 0x68, 0x000e);
  43         /* Enable LPC ROM range mirroring end at 0x000f(ffff). */
  44         pci_io_write_config16(dev, 0x6a, 0x000f);
  45
  46         /* LPC ROM address range 2: */
  47         /*
  48          * Enable LPC ROM range start at:
  49          * 0xfff8(0000): 512KB
  50          * 0xfff0(0000): 1MB
  51          * 0xffe0(0000): 2MB
  52          * 0xffc0(0000): 4MB
  53          */
  54         pci_io_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
  55         /* Enable LPC ROM range end at 0xffff(ffff). */
  56         pci_io_write_config16(dev, 0x6e, 0xffff);
  57 }
  58
  59 static void bootblock_southbridge_init(void)
  60 {
  61         hudson_enable_rom();
  62 }
  63
  64
  65 #if !CONFIG(ROMCC_BOOTBLOCK)
  66
  67 #include <bootblock_common.h>
  68 #include <amdblocks/acpimmio.h>
  69 #include <southbridge/amd/agesa/hudson/hudson.h>
  70
  71 void bootblock_soc_early_init(void)
  72 {
  73         pci_devfn_t dev;
  74         u32 data;
  75
  76         bootblock_southbridge_init();
  77         enable_acpimmio_decode_pm24();
  78         hudson_lpc_decode();
  79
  80         if (CONFIG(POST_DEVICE_PCI_PCIE))
  81                 hudson_pci_port80();
  82         else if (CONFIG(POST_DEVICE_LPC))
  83                 hudson_lpc_port80();
  84
  85         dev = PCI_DEV(0, 0x14, 3);
  86         data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE);
  87         /* enable 0x2e/0x4e IO decoding for SuperIO */
  88         pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3);
  89
  90         /*
  91          * Enable FCH to decode TPM associated Memory and IO regions for vboot
  92          *
  93          * Enable decoding of TPM cycles defined in TPM 1.2 spec
  94          * Enable decoding of legacy TPM addresses: IO addresses 0x7f-
  95          * 0x7e and 0xef-0xee.
  96          */
  97
  98         data = pci_read_config32(dev, LPC_TRUSTED_PLATFORM_MODULE);
  99         data |= TPM_12_EN | TPM_LEGACY_EN;
 100         pci_write_config32(dev, LPC_TRUSTED_PLATFORM_MODULE, data);
 101
 102         /*
 103          *  In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
 104          *  LpcClk[1:0]".  This following register setting has been
 105          *  replicated in every reference design since Parmer, so it is
 106          *  believed to be required even though it is not documented in
 107          *  the SoC BKDGs.  Without this setting, there is no serial
 108          *  output.
 109          */
 110         pm_write8(0xd2, 0);
 111 }
 112 #endif