src/drivers/xgi/common/vb_init.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 /* File taken from the Linux xgifb driver (v3.18.5) */
  15 /* coreboot related includes come indirectly from xgi_coreboot.h */
  16
  17 #include "xgi_coreboot.h"
  18 #include "vstruct.h"
  19 #include "XGIfb.h"
  20 #include "vb_def.h"
  21 #include "vb_util.h"
  22 #include "vb_setmode.h"
  23 #include "vb_init.h"
  24
  25 static const unsigned short XGINew_DDRDRAM_TYPE340[4][2] = {
  26         { 16, 0x45},
  27         {  8, 0x35},
  28         {  4, 0x31},
  29         {  2, 0x21} };
  30
  31 static const unsigned short XGINew_DDRDRAM_TYPE20[12][2] = {
  32         { 128, 0x5D},
  33         { 64, 0x59},
  34         { 64, 0x4D},
  35         { 32, 0x55},
  36         { 32, 0x49},
  37         { 32, 0x3D},
  38         { 16, 0x51},
  39         { 16, 0x45},
  40         { 16, 0x39},
  41         {  8, 0x41},
  42         {  8, 0x35},
  43         {  4, 0x31} };
  44
  45 #define XGIFB_ROM_SIZE  65536
  46
  47 static unsigned char
  48 XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
  49                        struct vb_device_info *pVBInfo)
  50 {
  51         unsigned char data, temp;
  52
  53         if (HwDeviceExtension->jChipType < XG20) {
  54                 data = xgifb_reg_get(pVBInfo->P3c4, 0x39) & 0x02;
  55                 if (data == 0)
  56                         data = (xgifb_reg_get(pVBInfo->P3c4, 0x3A) &
  57                                    0x02) >> 1;
  58                 return data;
  59         } else if (HwDeviceExtension->jChipType == XG27) {
  60                 temp = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
  61                 /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
  62                 if (((temp & 0x88) == 0x80) || ((temp & 0x88) == 0x08))
  63                         data = 0; /* DDR */
  64                 else
  65                         data = 1; /* DDRII */
  66                 return data;
  67         } else if (HwDeviceExtension->jChipType == XG21) {
  68                 /* Independent GPIO control */
  69                 xgifb_reg_and(pVBInfo->P3d4, 0xB4, ~0x02);
  70                 udelay(800);
  71                 xgifb_reg_or(pVBInfo->P3d4, 0x4A, 0x80); /* Enable GPIOH read */
  72                 /* GPIOF 0:DVI 1:DVO */
  73                 data = xgifb_reg_get(pVBInfo->P3d4, 0x48);
  74                 /* HOTPLUG_SUPPORT */
  75                 /* for current XG20 & XG21, GPIOH is floating, driver will
  76                  * fix DDR temporarily */
  77                 /* DVI read GPIOH */
  78                 data &= 0x01; /* 1=DDRII, 0=DDR */
  79                 /* ~HOTPLUG_SUPPORT */
  80                 xgifb_reg_or(pVBInfo->P3d4, 0xB4, 0x02);
  81                 return data;
  82         }
  83         data = xgifb_reg_get(pVBInfo->P3d4, 0x97) & 0x01;
  84
  85         if (data == 1)
  86                 data++;
  87
  88         return data;
  89 }
  90
  91 static void XGINew_DDR1x_MRS_340(unsigned long P3c4,
  92                                  struct vb_device_info *pVBInfo)
  93 {
  94         xgifb_reg_set(P3c4, 0x18, 0x01);
  95         xgifb_reg_set(P3c4, 0x19, 0x20);
  96         xgifb_reg_set(P3c4, 0x16, 0x00);
  97         xgifb_reg_set(P3c4, 0x16, 0x80);
  98
  99         mdelay(3);
 100         xgifb_reg_set(P3c4, 0x18, 0x00);
 101         xgifb_reg_set(P3c4, 0x19, 0x20);
 102         xgifb_reg_set(P3c4, 0x16, 0x00);
 103         xgifb_reg_set(P3c4, 0x16, 0x80);
 104
 105         udelay(60);
 106         xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
 107         xgifb_reg_set(P3c4, 0x19, 0x01);
 108         xgifb_reg_set(P3c4, 0x16, 0x03);
 109         xgifb_reg_set(P3c4, 0x16, 0x83);
 110         mdelay(1);
 111         xgifb_reg_set(P3c4, 0x1B, 0x03);
 112         udelay(500);
 113         xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
 114         xgifb_reg_set(P3c4, 0x19, 0x00);
 115         xgifb_reg_set(P3c4, 0x16, 0x03);
 116         xgifb_reg_set(P3c4, 0x16, 0x83);
 117         xgifb_reg_set(P3c4, 0x1B, 0x00);
 118 }
 119
 120 static void XGINew_SetMemoryClock(struct vb_device_info *pVBInfo)
 121 {
 122         xgifb_reg_set(pVBInfo->P3c4,
 123                       0x28,
 124                       pVBInfo->MCLKData[pVBInfo->ram_type].SR28);
 125         xgifb_reg_set(pVBInfo->P3c4,
 126                       0x29,
 127                       pVBInfo->MCLKData[pVBInfo->ram_type].SR29);
 128         xgifb_reg_set(pVBInfo->P3c4,
 129                       0x2A,
 130                       pVBInfo->MCLKData[pVBInfo->ram_type].SR2A);
 131
 132         xgifb_reg_set(pVBInfo->P3c4,
 133                       0x2E,
 134                       XGI340_ECLKData[pVBInfo->ram_type].SR2E);
 135         xgifb_reg_set(pVBInfo->P3c4,
 136                       0x2F,
 137                       XGI340_ECLKData[pVBInfo->ram_type].SR2F);
 138         xgifb_reg_set(pVBInfo->P3c4,
 139                       0x30,
 140                       XGI340_ECLKData[pVBInfo->ram_type].SR30);
 141 }
 142
 143 static void XGINew_DDRII_Bootup_XG27(
 144                         struct xgi_hw_device_info *HwDeviceExtension,
 145                         unsigned long P3c4, struct vb_device_info *pVBInfo)
 146 {
 147         unsigned long P3d4 = P3c4 + 0x10;
 148
 149         pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
 150         XGINew_SetMemoryClock(pVBInfo);
 151
 152         /* Set Double Frequency */
 153         xgifb_reg_set(P3d4, 0x97, pVBInfo->XGINew_CR97); /* CR97 */
 154
 155         udelay(200);
 156
 157         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS2 */
 158         xgifb_reg_set(P3c4, 0x19, 0x80); /* Set SR19 */
 159         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 160         udelay(15);
 161         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 162         udelay(15);
 163
 164         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS3 */
 165         xgifb_reg_set(P3c4, 0x19, 0xC0); /* Set SR19 */
 166         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 167         udelay(15);
 168         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 169         udelay(15);
 170
 171         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS1 */
 172         xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
 173         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 174         udelay(30);
 175         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 176         udelay(15);
 177
 178         xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Enable */
 179         xgifb_reg_set(P3c4, 0x19, 0x0A); /* Set SR19 */
 180         xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
 181         udelay(30);
 182         xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
 183         xgifb_reg_set(P3c4, 0x16, 0x80); /* Set SR16 */
 184
 185         xgifb_reg_set(P3c4, 0x1B, 0x04); /* Set SR1B */
 186         udelay(60);
 187         xgifb_reg_set(P3c4, 0x1B, 0x00); /* Set SR1B */
 188
 189         xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Reset */
 190         xgifb_reg_set(P3c4, 0x19, 0x08); /* Set SR19 */
 191         xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
 192
 193         udelay(30);
 194         xgifb_reg_set(P3c4, 0x16, 0x83); /* Set SR16 */
 195         udelay(15);
 196
 197         xgifb_reg_set(P3c4, 0x18, 0x80); /* Set SR18 */ /* MRS, ODT */
 198         xgifb_reg_set(P3c4, 0x19, 0x46); /* Set SR19 */
 199         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 200         udelay(30);
 201         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 202         udelay(15);
 203
 204         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS */
 205         xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
 206         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 207         udelay(30);
 208         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 209         udelay(15);
 210
 211         /* Set SR1B refresh control 000:close; 010:open */
 212         xgifb_reg_set(P3c4, 0x1B, 0x04);
 213         udelay(200);
 214
 215 }
 216
 217 static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
 218                 unsigned long P3c4, struct vb_device_info *pVBInfo)
 219 {
 220         unsigned long P3d4 = P3c4 + 0x10;
 221
 222         pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
 223         XGINew_SetMemoryClock(pVBInfo);
 224
 225         xgifb_reg_set(P3d4, 0x97, 0x11); /* CR97 */
 226
 227         udelay(200);
 228         xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS2 */
 229         xgifb_reg_set(P3c4, 0x19, 0x80);
 230         xgifb_reg_set(P3c4, 0x16, 0x05);
 231         xgifb_reg_set(P3c4, 0x16, 0x85);
 232
 233         xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS3 */
 234         xgifb_reg_set(P3c4, 0x19, 0xC0);
 235         xgifb_reg_set(P3c4, 0x16, 0x05);
 236         xgifb_reg_set(P3c4, 0x16, 0x85);
 237
 238         xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS1 */
 239         xgifb_reg_set(P3c4, 0x19, 0x40);
 240         xgifb_reg_set(P3c4, 0x16, 0x05);
 241         xgifb_reg_set(P3c4, 0x16, 0x85);
 242
 243         xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
 244         xgifb_reg_set(P3c4, 0x19, 0x02);
 245         xgifb_reg_set(P3c4, 0x16, 0x05);
 246         xgifb_reg_set(P3c4, 0x16, 0x85);
 247
 248         udelay(15);
 249         xgifb_reg_set(P3c4, 0x1B, 0x04); /* SR1B */
 250         udelay(30);
 251         xgifb_reg_set(P3c4, 0x1B, 0x00); /* SR1B */
 252         udelay(100);
 253
 254         xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
 255         xgifb_reg_set(P3c4, 0x19, 0x00);
 256         xgifb_reg_set(P3c4, 0x16, 0x05);
 257         xgifb_reg_set(P3c4, 0x16, 0x85);
 258
 259         udelay(200);
 260 }
 261
 262 static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4,
 263                                   struct vb_device_info *pVBInfo)
 264 {
 265         xgifb_reg_set(P3c4, 0x18, 0x01);
 266         xgifb_reg_set(P3c4, 0x19, 0x40);
 267         xgifb_reg_set(P3c4, 0x16, 0x00);
 268         xgifb_reg_set(P3c4, 0x16, 0x80);
 269         udelay(60);
 270
 271         xgifb_reg_set(P3c4, 0x18, 0x00);
 272         xgifb_reg_set(P3c4, 0x19, 0x40);
 273         xgifb_reg_set(P3c4, 0x16, 0x00);
 274         xgifb_reg_set(P3c4, 0x16, 0x80);
 275         udelay(60);
 276         xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
 277         xgifb_reg_set(P3c4, 0x19, 0x01);
 278         xgifb_reg_set(P3c4, 0x16, 0x03);
 279         xgifb_reg_set(P3c4, 0x16, 0x83);
 280         mdelay(1);
 281         xgifb_reg_set(P3c4, 0x1B, 0x03);
 282         udelay(500);
 283         xgifb_reg_set(P3c4, 0x18, pVBInfo->SR18[pVBInfo->ram_type]); /* SR18 */
 284         xgifb_reg_set(P3c4, 0x19, 0x00);
 285         xgifb_reg_set(P3c4, 0x16, 0x03);
 286         xgifb_reg_set(P3c4, 0x16, 0x83);
 287         xgifb_reg_set(P3c4, 0x1B, 0x00);
 288 }
 289
 290 static void XGINew_DDR1x_DefaultRegister(
 291                 struct xgi_hw_device_info *HwDeviceExtension,
 292                 unsigned long Port, struct vb_device_info *pVBInfo)
 293 {
 294         unsigned long P3d4 = Port, P3c4 = Port - 0x10;
 295
 296         if (HwDeviceExtension->jChipType >= XG20) {
 297                 XGINew_SetMemoryClock(pVBInfo);
 298                 xgifb_reg_set(P3d4,
 299                               0x82,
 300                               pVBInfo->CR40[11][pVBInfo->ram_type]); /* CR82 */
 301                 xgifb_reg_set(P3d4,
 302                               0x85,
 303                               pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
 304                 xgifb_reg_set(P3d4,
 305                               0x86,
 306                               pVBInfo->CR40[13][pVBInfo->ram_type]); /* CR86 */
 307
 308                 xgifb_reg_set(P3d4, 0x98, 0x01);
 309                 xgifb_reg_set(P3d4, 0x9A, 0x02);
 310
 311                 XGINew_DDR1x_MRS_XG20(P3c4, pVBInfo);
 312         } else {
 313                 XGINew_SetMemoryClock(pVBInfo);
 314
 315                 switch (HwDeviceExtension->jChipType) {
 316                 case XG42:
 317                         /* CR82 */
 318                         xgifb_reg_set(P3d4,
 319                                       0x82,
 320                                       pVBInfo->CR40[11][pVBInfo->ram_type]);
 321                         /* CR85 */
 322                         xgifb_reg_set(P3d4,
 323                                       0x85,
 324                                       pVBInfo->CR40[12][pVBInfo->ram_type]);
 325                         /* CR86 */
 326                         xgifb_reg_set(P3d4,
 327                                       0x86,
 328                                       pVBInfo->CR40[13][pVBInfo->ram_type]);
 329                         break;
 330                 default:
 331                         xgifb_reg_set(P3d4, 0x82, 0x88);
 332                         xgifb_reg_set(P3d4, 0x86, 0x00);
 333                         /* Insert read command for delay */
 334                         xgifb_reg_get(P3d4, 0x86);
 335                         xgifb_reg_set(P3d4, 0x86, 0x88);
 336                         xgifb_reg_get(P3d4, 0x86);
 337                         xgifb_reg_set(P3d4,
 338                                       0x86,
 339                                       pVBInfo->CR40[13][pVBInfo->ram_type]);
 340                         xgifb_reg_set(P3d4, 0x82, 0x77);
 341                         xgifb_reg_set(P3d4, 0x85, 0x00);
 342
 343                         /* Insert read command for delay */
 344                         xgifb_reg_get(P3d4, 0x85);
 345                         xgifb_reg_set(P3d4, 0x85, 0x88);
 346
 347                         /* Insert read command for delay */
 348                         xgifb_reg_get(P3d4, 0x85);
 349                         /* CR85 */
 350                         xgifb_reg_set(P3d4,
 351                                       0x85,
 352                                       pVBInfo->CR40[12][pVBInfo->ram_type]);
 353                         /* CR82 */
 354                         xgifb_reg_set(P3d4,
 355                                       0x82,
 356                                       pVBInfo->CR40[11][pVBInfo->ram_type]);
 357                         break;
 358                 }
 359
 360                 xgifb_reg_set(P3d4, 0x97, 0x00);
 361                 xgifb_reg_set(P3d4, 0x98, 0x01);
 362                 xgifb_reg_set(P3d4, 0x9A, 0x02);
 363                 XGINew_DDR1x_MRS_340(P3c4, pVBInfo);
 364         }
 365 }
 366
 367 static void XGINew_DDR2_DefaultRegister(
 368                 struct xgi_hw_device_info *HwDeviceExtension,
 369                 unsigned long Port, struct vb_device_info *pVBInfo)
 370 {
 371         unsigned long P3d4 = Port, P3c4 = Port - 0x10;
 372
 373         /* keep following setting sequence, each setting in
 374          * the same reg insert idle */
 375         xgifb_reg_set(P3d4, 0x82, 0x77);
 376         xgifb_reg_set(P3d4, 0x86, 0x00);
 377         xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
 378         xgifb_reg_set(P3d4, 0x86, 0x88);
 379         xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
 380         /* CR86 */
 381         xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][pVBInfo->ram_type]);
 382         xgifb_reg_set(P3d4, 0x82, 0x77);
 383         xgifb_reg_set(P3d4, 0x85, 0x00);
 384         xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
 385         xgifb_reg_set(P3d4, 0x85, 0x88);
 386         xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
 387         xgifb_reg_set(P3d4,
 388                       0x85,
 389                       pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
 390         if (HwDeviceExtension->jChipType == XG27)
 391                 /* CR82 */
 392                 xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][pVBInfo->ram_type]);
 393         else
 394                 xgifb_reg_set(P3d4, 0x82, 0xA8); /* CR82 */
 395
 396         xgifb_reg_set(P3d4, 0x98, 0x01);
 397         xgifb_reg_set(P3d4, 0x9A, 0x02);
 398         if (HwDeviceExtension->jChipType == XG27)
 399                 XGINew_DDRII_Bootup_XG27(HwDeviceExtension, P3c4, pVBInfo);
 400         else
 401                 XGINew_DDR2_MRS_XG20(HwDeviceExtension, P3c4, pVBInfo);
 402 }
 403
 404 static void XGI_SetDRAM_Helper(unsigned long P3d4, u8 seed, u8 temp2, u8 reg,
 405         u8 shift_factor, u8 mask1, u8 mask2)
 406 {
 407         u8 j;
 408
 409         for (j = 0; j < 4; j++) {
 410                 temp2 |= (((seed >> (2 * j)) & 0x03) << shift_factor);
 411                 xgifb_reg_set(P3d4, reg, temp2);
 412                 xgifb_reg_get(P3d4, reg);
 413                 temp2 &= mask1;
 414                 temp2 += mask2;
 415         }
 416 }
 417
 418 static void XGINew_SetDRAMDefaultRegister340(
 419                 struct xgi_hw_device_info *HwDeviceExtension,
 420                 unsigned long Port, struct vb_device_info *pVBInfo)
 421 {
 422         unsigned char temp, temp1, temp2, temp3, j, k;
 423
 424         unsigned long P3d4 = Port, P3c4 = Port - 0x10;
 425
 426         xgifb_reg_set(P3d4, 0x6D, pVBInfo->CR40[8][pVBInfo->ram_type]);
 427         xgifb_reg_set(P3d4, 0x68, pVBInfo->CR40[5][pVBInfo->ram_type]);
 428         xgifb_reg_set(P3d4, 0x69, pVBInfo->CR40[6][pVBInfo->ram_type]);
 429         xgifb_reg_set(P3d4, 0x6A, pVBInfo->CR40[7][pVBInfo->ram_type]);
 430
 431         /* CR6B DQS fine tune delay */
 432         temp = 0xaa;
 433         XGI_SetDRAM_Helper(P3d4, temp, 0, 0x6B, 2, 0xF0, 0x10);
 434
 435         /* CR6E DQM fine tune delay */
 436         XGI_SetDRAM_Helper(P3d4, 0, 0, 0x6E, 2, 0xF0, 0x10);
 437
 438         temp3 = 0;
 439         for (k = 0; k < 4; k++) {
 440                 /* CR6E_D[1:0] select channel */
 441                 xgifb_reg_and_or(P3d4, 0x6E, 0xFC, temp3);
 442                 XGI_SetDRAM_Helper(P3d4, 0, 0, 0x6F, 0, 0xF8, 0x08);
 443                 temp3 += 0x01;
 444         }
 445
 446         xgifb_reg_set(P3d4,
 447                       0x80,
 448                       pVBInfo->CR40[9][pVBInfo->ram_type]); /* CR80 */
 449         xgifb_reg_set(P3d4,
 450                       0x81,
 451                       pVBInfo->CR40[10][pVBInfo->ram_type]); /* CR81 */
 452
 453         temp2 = 0x80;
 454         /* CR89 terminator type select */
 455         XGI_SetDRAM_Helper(P3d4, 0, temp2, 0x89, 0, 0xF0, 0x10);
 456
 457         temp = 0;
 458         temp1 = temp & 0x03;
 459         temp2 |= temp1;
 460         xgifb_reg_set(P3d4, 0x89, temp2);
 461
 462         temp = pVBInfo->CR40[3][pVBInfo->ram_type];
 463         temp1 = temp & 0x0F;
 464         temp2 = (temp >> 4) & 0x07;
 465         temp3 = temp & 0x80;
 466         xgifb_reg_set(P3d4, 0x45, temp1); /* CR45 */
 467         xgifb_reg_set(P3d4, 0x99, temp2); /* CR99 */
 468         xgifb_reg_or(P3d4, 0x40, temp3); /* CR40_D[7] */
 469         xgifb_reg_set(P3d4,
 470                       0x41,
 471                       pVBInfo->CR40[0][pVBInfo->ram_type]); /* CR41 */
 472
 473         if (HwDeviceExtension->jChipType == XG27)
 474                 xgifb_reg_set(P3d4, 0x8F, XG27_CR8F); /* CR8F */
 475
 476         for (j = 0; j <= 6; j++) /* CR90 - CR96 */
 477                 xgifb_reg_set(P3d4, (0x90 + j),
 478                                 pVBInfo->CR40[14 + j][pVBInfo->ram_type]);
 479
 480         for (j = 0; j <= 2; j++) /* CRC3 - CRC5 */
 481                 xgifb_reg_set(P3d4, (0xC3 + j),
 482                                 pVBInfo->CR40[21 + j][pVBInfo->ram_type]);
 483
 484         for (j = 0; j < 2; j++) /* CR8A - CR8B */
 485                 xgifb_reg_set(P3d4, (0x8A + j),
 486                                 pVBInfo->CR40[1 + j][pVBInfo->ram_type]);
 487
 488         if (HwDeviceExtension->jChipType == XG42)
 489                 xgifb_reg_set(P3d4, 0x8C, 0x87);
 490
 491         xgifb_reg_set(P3d4,
 492                       0x59,
 493                       pVBInfo->CR40[4][pVBInfo->ram_type]); /* CR59 */
 494
 495         xgifb_reg_set(P3d4, 0x83, 0x09); /* CR83 */
 496         xgifb_reg_set(P3d4, 0x87, 0x00); /* CR87 */
 497         xgifb_reg_set(P3d4, 0xCF, XG40_CRCF); /* CRCF */
 498         if (pVBInfo->ram_type) {
 499                 xgifb_reg_set(P3c4, 0x17, 0x80); /* SR17 DDRII */
 500                 if (HwDeviceExtension->jChipType == XG27)
 501                         xgifb_reg_set(P3c4, 0x17, 0x02); /* SR17 DDRII */
 502
 503         } else {
 504                 xgifb_reg_set(P3c4, 0x17, 0x00); /* SR17 DDR */
 505         }
 506         xgifb_reg_set(P3c4, 0x1A, 0x87); /* SR1A */
 507
 508         temp = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
 509         if (temp == 0) {
 510                 XGINew_DDR1x_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
 511         } else {
 512                 xgifb_reg_set(P3d4, 0xB0, 0x80); /* DDRII Dual frequency mode */
 513                 XGINew_DDR2_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
 514         }
 515         xgifb_reg_set(P3c4, 0x1B, 0x03); /* SR1B */
 516 }
 517
 518
 519 static unsigned short XGINew_SetDRAMSize20Reg(
 520                 unsigned short dram_size,
 521                 struct vb_device_info *pVBInfo)
 522 {
 523         unsigned short data = 0, memsize = 0;
 524         int RankSize;
 525         unsigned char ChannelNo;
 526
 527         RankSize = dram_size * pVBInfo->ram_bus / 8;
 528         data = xgifb_reg_get(pVBInfo->P3c4, 0x13);
 529         data &= 0x80;
 530
 531         if (data == 0x80)
 532                 RankSize *= 2;
 533
 534         data = 0;
 535
 536         if (pVBInfo->ram_channel == 3)
 537                 ChannelNo = 4;
 538         else
 539                 ChannelNo = pVBInfo->ram_channel;
 540
 541         if (ChannelNo * RankSize <= 256) {
 542                 while ((RankSize >>= 1) > 0)
 543                         data += 0x10;
 544
 545                 memsize = data >> 4;
 546
 547                 /* Fix DRAM Sizing Error */
 548                 xgifb_reg_set(pVBInfo->P3c4,
 549                               0x14,
 550                               (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
 551                                 (data & 0xF0));
 552                 udelay(15);
 553         }
 554         return memsize;
 555 }
 556
 557 static int XGINew_ReadWriteRest(unsigned short StopAddr,
 558                 unsigned short StartAddr, struct vb_device_info *pVBInfo)
 559 {
 560         int i;
 561         unsigned long Position = 0;
 562         void __iomem *fbaddr = pVBInfo->FBAddr;
 563
 564         write32(fbaddr + Position, Position);
 565
 566         for (i = StartAddr; i <= StopAddr; i++) {
 567                 Position = 1 << i;
 568                 write32(fbaddr + Position, Position);
 569         }
 570
 571         udelay(500); /* Fix #1759 Memory Size error in Multi-Adapter. */
 572
 573         Position = 0;
 574
 575         if (read32(fbaddr + Position) != Position)
 576                 return 0;
 577
 578         for (i = StartAddr; i <= StopAddr; i++) {
 579                 Position = 1 << i;
 580                 if (read32(fbaddr + Position) != Position)
 581                         return 0;
 582         }
 583         return 1;
 584 }
 585
 586 static unsigned char XGINew_CheckFrequence(struct vb_device_info *pVBInfo)
 587 {
 588         unsigned char data;
 589
 590         data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
 591
 592         if ((data & 0x10) == 0) {
 593                 data = xgifb_reg_get(pVBInfo->P3c4, 0x39);
 594                 data = (data & 0x02) >> 1;
 595                 return data;
 596         }
 597         return data & 0x01;
 598 }
 599
 600 static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
 601                 struct vb_device_info *pVBInfo)
 602 {
 603         unsigned char data;
 604
 605         switch (HwDeviceExtension->jChipType) {
 606         case XG20:
 607         case XG21:
 608                 data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
 609                 data = data & 0x01;
 610                 pVBInfo->ram_channel = 1; /* XG20 "JUST" one channel */
 611
 612                 if (data == 0) { /* Single_32_16 */
 613
 614                         if ((HwDeviceExtension->ulVideoMemorySize - 1)
 615                                         > 0x1000000) {
 616
 617                                 pVBInfo->ram_bus = 32; /* 32 bits */
 618                                 /* 22bit + 2 rank + 32bit */
 619                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 620                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
 621                                 udelay(15);
 622
 623                                 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 624                                         return;
 625
 626                                 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 627                                     0x800000) {
 628                                         /* 22bit + 1 rank + 32bit */
 629                                         xgifb_reg_set(pVBInfo->P3c4,
 630                                                       0x13,
 631                                                       0x31);
 632                                         xgifb_reg_set(pVBInfo->P3c4,
 633                                                       0x14,
 634                                                       0x42);
 635                                         udelay(15);
 636
 637                                         if (XGINew_ReadWriteRest(23,
 638                                                                  23,
 639                                                                  pVBInfo) == 1)
 640                                                 return;
 641                                 }
 642                         }
 643
 644                         if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 645                             0x800000) {
 646                                 pVBInfo->ram_bus = 16; /* 16 bits */
 647                                 /* 22bit + 2 rank + 16bit */
 648                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 649                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
 650                                 udelay(15);
 651
 652                                 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 653                                         return;
 654                                 xgifb_reg_set(pVBInfo->P3c4,
 655                                               0x13,
 656                                               0x31);
 657                                 udelay(15);
 658                         }
 659
 660                 } else { /* Dual_16_8 */
 661                         if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 662                             0x800000) {
 663                                 pVBInfo->ram_bus = 16; /* 16 bits */
 664                                 /* (0x31:12x8x2) 22bit + 2 rank */
 665                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 666                                 /* 0x41:16Mx16 bit*/
 667                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
 668                                 udelay(15);
 669
 670                                 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 671                                         return;
 672
 673                                 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 674                                     0x400000) {
 675                                         /* (0x31:12x8x2) 22bit + 1 rank */
 676                                         xgifb_reg_set(pVBInfo->P3c4,
 677                                                       0x13,
 678                                                       0x31);
 679                                         /* 0x31:8Mx16 bit*/
 680                                         xgifb_reg_set(pVBInfo->P3c4,
 681                                                       0x14,
 682                                                       0x31);
 683                                         udelay(15);
 684
 685                                         if (XGINew_ReadWriteRest(22,
 686                                                                  22,
 687                                                                  pVBInfo) == 1)
 688                                                 return;
 689                                 }
 690                         }
 691
 692                         if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 693                             0x400000) {
 694                                 pVBInfo->ram_bus = 8; /* 8 bits */
 695                                 /* (0x31:12x8x2) 22bit + 2 rank */
 696                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 697                                 /* 0x30:8Mx8 bit*/
 698                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
 699                                 udelay(15);
 700
 701                                 if (XGINew_ReadWriteRest(22, 21, pVBInfo) == 1)
 702                                         return;
 703
 704                                 /* (0x31:12x8x2) 22bit + 1 rank */
 705                                 xgifb_reg_set(pVBInfo->P3c4,
 706                                               0x13,
 707                                               0x31);
 708                                 udelay(15);
 709                         }
 710                 }
 711                 break;
 712
 713         case XG27:
 714                 pVBInfo->ram_bus = 16; /* 16 bits */
 715                 pVBInfo->ram_channel = 1; /* Single channel */
 716                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x51); /* 32Mx16 bit*/
 717                 break;
 718         case XG42:
 719                 /*
 720                  XG42 SR14 D[3] Reserve
 721                  D[2] = 1, Dual Channel
 722                  = 0, Single Channel
 723
 724                  It's Different from Other XG40 Series.
 725                  */
 726                 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII, DDR2x */
 727                         pVBInfo->ram_bus = 32; /* 32 bits */
 728                         pVBInfo->ram_channel = 2; /* 2 Channel */
 729                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 730                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x44);
 731
 732                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 733                                 return;
 734
 735                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 736                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x34);
 737                         if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 738                                 return;
 739
 740                         pVBInfo->ram_channel = 1; /* Single Channel */
 741                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 742                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x40);
 743
 744                         if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 745                                 return;
 746                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 747                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
 748                 } else { /* DDR */
 749                         pVBInfo->ram_bus = 64; /* 64 bits */
 750                         pVBInfo->ram_channel = 1; /* 1 channels */
 751                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 752                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
 753
 754                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 755                                 return;
 756                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 757                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);
 758                 }
 759
 760                 break;
 761
 762         default: /* XG40 */
 763
 764                 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII */
 765                         pVBInfo->ram_bus = 32; /* 32 bits */
 766                         pVBInfo->ram_channel = 3;
 767                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 768                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C);
 769
 770                         if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
 771                                 return;
 772
 773                         pVBInfo->ram_channel = 2; /* 2 channels */
 774                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48);
 775
 776                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 777                                 return;
 778
 779                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 780                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C);
 781
 782                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1) {
 783                                 pVBInfo->ram_channel = 3; /* 4 channels */
 784                         } else {
 785                                 pVBInfo->ram_channel = 2; /* 2 channels */
 786                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38);
 787                         }
 788                 } else { /* DDR */
 789                         pVBInfo->ram_bus = 64; /* 64 bits */
 790                         pVBInfo->ram_channel = 2; /* 2 channels */
 791                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 792                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A);
 793
 794                         if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1)
 795                                 return;
 796                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 797                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A);
 798                 }
 799                 break;
 800         }
 801 }
 802
 803 static int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension,
 804                 struct vb_device_info *pVBInfo)
 805 {
 806         u8 i, size;
 807         unsigned short memsize, start_addr;
 808         const unsigned short (*dram_table)[2];
 809
 810         xgifb_reg_set(pVBInfo->P3c4, 0x15, 0x00); /* noninterleaving */
 811         xgifb_reg_set(pVBInfo->P3c4, 0x1C, 0x00); /* nontiling */
 812         XGINew_CheckChannel(HwDeviceExtension, pVBInfo);
 813
 814         if (HwDeviceExtension->jChipType >= XG20) {
 815                 dram_table = XGINew_DDRDRAM_TYPE20;
 816                 size = ARRAY_SIZE(XGINew_DDRDRAM_TYPE20);
 817                 start_addr = 5;
 818         } else {
 819                 dram_table = XGINew_DDRDRAM_TYPE340;
 820                 size = ARRAY_SIZE(XGINew_DDRDRAM_TYPE340);
 821                 start_addr = 9;
 822         }
 823
 824         for (i = 0; i < size; i++) {
 825                 /* SetDRAMSizingType */
 826                 xgifb_reg_and_or(pVBInfo->P3c4, 0x13, 0x80, dram_table[i][1]);
 827                 udelay(15); /* should delay 50 ns */
 828
 829                 memsize = XGINew_SetDRAMSize20Reg(dram_table[i][0], pVBInfo);
 830
 831                 if (memsize == 0)
 832                         continue;
 833
 834                 memsize += (pVBInfo->ram_channel - 2) + 20;
 835                 if ((HwDeviceExtension->ulVideoMemorySize - 1) <
 836                         (unsigned long) (1 << memsize))
 837                         continue;
 838
 839                 if (XGINew_ReadWriteRest(memsize, start_addr, pVBInfo) == 1)
 840                         return 1;
 841         }
 842         return 0;
 843 }
 844
 845 static void XGINew_SetDRAMSize_340(struct xgifb_video_info *xgifb_info,
 846                 struct xgi_hw_device_info *HwDeviceExtension,
 847                 struct vb_device_info *pVBInfo)
 848 {
 849         unsigned short data;
 850
 851         pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
 852
 853         if (CONFIG(LINEAR_FRAMEBUFFER))
 854                 XGISetModeNew(xgifb_info, HwDeviceExtension, 0x2e);
 855
 856         data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
 857         /* disable read cache */
 858         xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data & 0xDF));
 859         XGI_DisplayOff(xgifb_info, HwDeviceExtension, pVBInfo);
 860
 861         XGINew_DDRSizing340(HwDeviceExtension, pVBInfo);
 862         data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
 863         /* enable read cache */
 864         xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data | 0x20));
 865 }
 866
 867 static void XGINew_ChkSenseStatus(struct vb_device_info *pVBInfo)
 868 {
 869         unsigned short tempbx = 0, temp, tempcx, CR3CData;
 870
 871         temp = xgifb_reg_get(pVBInfo->P3d4, 0x32);
 872
 873         if (temp & Monitor1Sense)
 874                 tempbx |= ActiveCRT1;
 875         if (temp & LCDSense)
 876                 tempbx |= ActiveLCD;
 877         if (temp & Monitor2Sense)
 878                 tempbx |= ActiveCRT2;
 879         if (temp & TVSense) {
 880                 tempbx |= ActiveTV;
 881                 if (temp & AVIDEOSense)
 882                         tempbx |= (ActiveAVideo << 8);
 883                 if (temp & SVIDEOSense)
 884                         tempbx |= (ActiveSVideo << 8);
 885                 if (temp & SCARTSense)
 886                         tempbx |= (ActiveSCART << 8);
 887                 if (temp & HiTVSense)
 888                         tempbx |= (ActiveHiTV << 8);
 889                 if (temp & YPbPrSense)
 890                         tempbx |= (ActiveYPbPr << 8);
 891         }
 892
 893         tempcx = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
 894         tempcx |= (xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8);
 895
 896         if (tempbx & tempcx) {
 897                 CR3CData = xgifb_reg_get(pVBInfo->P3d4, 0x3c);
 898                 if (!(CR3CData & DisplayDeviceFromCMOS))
 899                         tempcx = 0x1FF0;
 900         } else {
 901                 tempcx = 0x1FF0;
 902         }
 903
 904         tempbx &= tempcx;
 905         xgifb_reg_set(pVBInfo->P3d4, 0x3d, (tempbx & 0x00FF));
 906         xgifb_reg_set(pVBInfo->P3d4, 0x3e, ((tempbx & 0xFF00) >> 8));
 907 }
 908
 909 static void XGINew_SetModeScratch(struct vb_device_info *pVBInfo)
 910 {
 911         unsigned short temp, tempcl = 0, tempch = 0, CR31Data, CR38Data;
 912
 913         temp = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
 914         temp |= xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8;
 915         temp |= (xgifb_reg_get(pVBInfo->P3d4, 0x31) & (DriverMode >> 8)) << 8;
 916
 917         if (pVBInfo->IF_DEF_CRT2Monitor == 1) {
 918                 if (temp & ActiveCRT2)
 919                         tempcl = SetCRT2ToRAMDAC;
 920         }
 921
 922         if (temp & ActiveLCD) {
 923                 tempcl |= SetCRT2ToLCD;
 924                 if (temp & DriverMode) {
 925                         if (temp & ActiveTV) {
 926                                 tempch = SetToLCDA | EnableDualEdge;
 927                                 temp ^= SetCRT2ToLCD;
 928
 929                                 if ((temp >> 8) & ActiveAVideo)
 930                                         tempcl |= SetCRT2ToAVIDEO;
 931                                 if ((temp >> 8) & ActiveSVideo)
 932                                         tempcl |= SetCRT2ToSVIDEO;
 933                                 if ((temp >> 8) & ActiveSCART)
 934                                         tempcl |= SetCRT2ToSCART;
 935
 936                                 if (pVBInfo->IF_DEF_HiVision == 1) {
 937                                         if ((temp >> 8) & ActiveHiTV)
 938                                                 tempcl |= SetCRT2ToHiVision;
 939                                 }
 940
 941                                 if (pVBInfo->IF_DEF_YPbPr == 1) {
 942                                         if ((temp >> 8) & ActiveYPbPr)
 943                                                 tempch |= SetYPbPr;
 944                                 }
 945                         }
 946                 }
 947         } else {
 948                 if ((temp >> 8) & ActiveAVideo)
 949                         tempcl |= SetCRT2ToAVIDEO;
 950                 if ((temp >> 8) & ActiveSVideo)
 951                         tempcl |= SetCRT2ToSVIDEO;
 952                 if ((temp >> 8) & ActiveSCART)
 953                         tempcl |= SetCRT2ToSCART;
 954
 955                 if (pVBInfo->IF_DEF_HiVision == 1) {
 956                         if ((temp >> 8) & ActiveHiTV)
 957                                 tempcl |= SetCRT2ToHiVision;
 958                 }
 959
 960                 if (pVBInfo->IF_DEF_YPbPr == 1) {
 961                         if ((temp >> 8) & ActiveYPbPr)
 962                                 tempch |= SetYPbPr;
 963                 }
 964         }
 965
 966         tempcl |= SetSimuScanMode;
 967         if ((!(temp & ActiveCRT1)) && ((temp & ActiveLCD) || (temp & ActiveTV)
 968                         || (temp & ActiveCRT2)))
 969                 tempcl ^= (SetSimuScanMode | SwitchCRT2);
 970         if ((temp & ActiveLCD) && (temp & ActiveTV))
 971                 tempcl ^= (SetSimuScanMode | SwitchCRT2);
 972         xgifb_reg_set(pVBInfo->P3d4, 0x30, tempcl);
 973
 974         CR31Data = xgifb_reg_get(pVBInfo->P3d4, 0x31);
 975         CR31Data &= ~(SetNotSimuMode >> 8);
 976         if (!(temp & ActiveCRT1))
 977                 CR31Data |= (SetNotSimuMode >> 8);
 978         CR31Data &= ~(DisableCRT2Display >> 8);
 979         if (!((temp & ActiveLCD) || (temp & ActiveTV) || (temp & ActiveCRT2)))
 980                 CR31Data |= (DisableCRT2Display >> 8);
 981         xgifb_reg_set(pVBInfo->P3d4, 0x31, CR31Data);
 982
 983         CR38Data = xgifb_reg_get(pVBInfo->P3d4, 0x38);
 984         CR38Data &= ~SetYPbPr;
 985         CR38Data |= tempch;
 986         xgifb_reg_set(pVBInfo->P3d4, 0x38, CR38Data);
 987
 988 }
 989
 990 static unsigned short XGINew_SenseLCD(struct xgi_hw_device_info
 991                                                         *HwDeviceExtension,
 992                                       struct vb_device_info *pVBInfo)
 993 {
 994         unsigned short temp = HwDeviceExtension->ulCRT2LCDType;
 995
 996         switch (HwDeviceExtension->ulCRT2LCDType) {
 997         case LCD_640x480:
 998         case LCD_1024x600:
 999         case LCD_1152x864:
1000         case LCD_1280x960:
1001         case LCD_1152x768:
1002         case LCD_1920x1440:
1003         case LCD_2048x1536:
1004                 temp = 0; /* overwrite used ulCRT2LCDType */
1005                 break;
1006         case LCD_UNKNOWN: /* unknown lcd, do nothing */
1007                 return 0;
1008         }
1009         xgifb_reg_and_or(pVBInfo->P3d4, 0x36, 0xF0, temp);
1010         return 1;
1011 }
1012
1013 static void XGINew_GetXG21Sense(struct pci_dev *pdev,
1014                 struct vb_device_info *pVBInfo)
1015 {
1016         struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
1017         unsigned char Temp;
1018
1019         /* Enable GPIOA/B read  */
1020         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1021         Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0xC0;
1022         if (Temp == 0xC0) { /* DVI & DVO GPIOA/B pull high */
1023                 XGINew_SenseLCD(&xgifb_info->hw_info, pVBInfo);
1024                 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1025                 /* Enable read GPIOF */
1026                 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x20, 0x20);
1027                 if (xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x04)
1028                         Temp = 0xA0; /* Only DVO on chip */
1029                 else
1030                         Temp = 0x80; /* TMDS on chip */
1031                 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, Temp);
1032                 /* Disable read GPIOF */
1033                 xgifb_reg_and(pVBInfo->P3d4, 0x4A, ~0x20);
1034         }
1035 }
1036
1037 static void XGINew_GetXG27Sense(struct vb_device_info *pVBInfo)
1038 {
1039         unsigned char Temp, bCR4A;
1040
1041         bCR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1042         /* Enable GPIOA/B/C read  */
1043         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x07, 0x07);
1044         Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x07;
1045         xgifb_reg_set(pVBInfo->P3d4, 0x4A, bCR4A);
1046
1047         if (Temp <= 0x02) {
1048                 /* LVDS setting */
1049                 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1050                 xgifb_reg_set(pVBInfo->P3d4, 0x30, 0x21);
1051         } else {
1052                 /* TMDS/DVO setting */
1053                 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0);
1054         }
1055         xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1056
1057 }
1058
1059 static unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo)
1060 {
1061         unsigned char CR38, CR4A, temp;
1062
1063         CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1064         /* enable GPIOE read */
1065         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x10, 0x10);
1066         CR38 = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1067         temp = 0;
1068         if ((CR38 & 0xE0) > 0x80) {
1069                 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1070                 temp &= 0x08;
1071                 temp >>= 3;
1072         }
1073
1074         xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1075
1076         return temp;
1077 }
1078
1079 static unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo)
1080 {
1081         unsigned char CR4A, temp;
1082
1083         CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1084         /* enable GPIOA/B/C read */
1085         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1086         temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1087         if (temp > 2)
1088                 temp = ((temp & 0x04) >> 1) | ((~temp) & 0x01);
1089
1090         xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1091
1092         return temp;
1093 }
1094
1095 static bool xgifb_bridge_is_on(struct vb_device_info *vb_info)
1096 {
1097         u8 flag;
1098
1099         flag = xgifb_reg_get(vb_info->Part4Port, 0x00);
1100         return flag == 1 || flag == 2;
1101 }
1102
1103 unsigned char XGIInitNew(struct pci_dev *pdev)
1104 {
1105         struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
1106         struct xgi_hw_device_info *HwDeviceExtension = &xgifb_info->hw_info;
1107         struct vb_device_info VBINF;
1108         struct vb_device_info *pVBInfo = &VBINF;
1109         unsigned char i, temp = 0, temp1;
1110
1111         pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
1112
1113         if (pVBInfo->FBAddr == NULL) {
1114                 dev_dbg(&pdev->dev, "pVBInfo->FBAddr == 0\n");
1115                 return 0;
1116         }
1117
1118         XGIRegInit(pVBInfo, xgifb_info->vga_base);
1119
1120         outb(0x67, pVBInfo->P3c2);
1121
1122         InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
1123
1124         /* Openkey */
1125         xgifb_reg_set(pVBInfo->P3c4, 0x05, 0x86);
1126
1127         /* GetXG21Sense (GPIO) */
1128         if (HwDeviceExtension->jChipType == XG21)
1129                 XGINew_GetXG21Sense(pdev, pVBInfo);
1130
1131         if (HwDeviceExtension->jChipType == XG27)
1132                 XGINew_GetXG27Sense(pVBInfo);
1133
1134         /* Reset Extended register */
1135
1136         for (i = 0x06; i < 0x20; i++)
1137                 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1138
1139         for (i = 0x21; i <= 0x27; i++)
1140                 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1141
1142         for (i = 0x31; i <= 0x3B; i++)
1143                 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1144
1145         /* Auto over driver for XG42 */
1146         if (HwDeviceExtension->jChipType == XG42)
1147                 xgifb_reg_set(pVBInfo->P3c4, 0x3B, 0xC0);
1148
1149         for (i = 0x79; i <= 0x7C; i++)
1150                 xgifb_reg_set(pVBInfo->P3d4, i, 0);
1151
1152         if (HwDeviceExtension->jChipType >= XG20)
1153                 xgifb_reg_set(pVBInfo->P3d4, 0x97, pVBInfo->XGINew_CR97);
1154
1155         /* SetDefExt1Regs begin */
1156         xgifb_reg_set(pVBInfo->P3c4, 0x07, XGI330_SR07);
1157         if (HwDeviceExtension->jChipType == XG27) {
1158                 xgifb_reg_set(pVBInfo->P3c4, 0x40, XG27_SR40);
1159                 xgifb_reg_set(pVBInfo->P3c4, 0x41, XG27_SR41);
1160         }
1161         xgifb_reg_set(pVBInfo->P3c4, 0x11, 0x0F);
1162         xgifb_reg_set(pVBInfo->P3c4, 0x1F, XGI330_SR1F);
1163         /* Frame buffer can read/write SR20 */
1164         xgifb_reg_set(pVBInfo->P3c4, 0x20, 0xA0);
1165         /* H/W request for slow corner chip */
1166         xgifb_reg_set(pVBInfo->P3c4, 0x36, 0x70);
1167         if (HwDeviceExtension->jChipType == XG27)
1168                 xgifb_reg_set(pVBInfo->P3c4, 0x36, XG27_SR36);
1169
1170         if (HwDeviceExtension->jChipType < XG20) {
1171                 u32 Temp;
1172
1173                 /* Set AGP customize registers (in SetDefAGPRegs) Start */
1174                 for (i = 0x47; i <= 0x4C; i++)
1175                         xgifb_reg_set(pVBInfo->P3d4,
1176                                       i,
1177                                       XGI340_AGPReg[i - 0x47]);
1178
1179                 for (i = 0x70; i <= 0x71; i++)
1180                         xgifb_reg_set(pVBInfo->P3d4,
1181                                       i,
1182                                       XGI340_AGPReg[6 + i - 0x70]);
1183
1184                 for (i = 0x74; i <= 0x77; i++)
1185                         xgifb_reg_set(pVBInfo->P3d4,
1186                                       i,
1187                                       XGI340_AGPReg[8 + i - 0x74]);
1188
1189                 pci_read_config_dword(pdev, 0x50, &Temp);
1190                 Temp >>= 20;
1191                 Temp &= 0xF;
1192
1193                 if (Temp == 1)
1194                         xgifb_reg_set(pVBInfo->P3d4, 0x48, 0x20); /* CR48 */
1195         } /* != XG20 */
1196
1197         /* Set PCI */
1198         xgifb_reg_set(pVBInfo->P3c4, 0x23, XGI330_SR23);
1199         xgifb_reg_set(pVBInfo->P3c4, 0x24, XGI330_SR24);
1200         xgifb_reg_set(pVBInfo->P3c4, 0x25, 0);
1201
1202         if (HwDeviceExtension->jChipType < XG20) {
1203                 /* Set VB */
1204                 XGI_UnLockCRT2(pVBInfo);
1205                 /* disable VideoCapture */
1206                 xgifb_reg_and_or(pVBInfo->Part0Port, 0x3F, 0xEF, 0x00);
1207                 xgifb_reg_set(pVBInfo->Part1Port, 0x00, 0x00);
1208                 /* chk if BCLK>=100MHz */
1209                 temp1 = xgifb_reg_get(pVBInfo->P3d4, 0x7B);
1210
1211                 xgifb_reg_set(pVBInfo->Part1Port,
1212                               0x02, XGI330_CRT2Data_1_2);
1213
1214                 xgifb_reg_set(pVBInfo->Part1Port, 0x2E, 0x08); /* use VB */
1215         } /* != XG20 */
1216
1217         xgifb_reg_set(pVBInfo->P3c4, 0x27, 0x1F);
1218
1219         if ((HwDeviceExtension->jChipType == XG42) &&
1220             XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) != 0) {
1221                 /* Not DDR */
1222                 xgifb_reg_set(pVBInfo->P3c4,
1223                               0x31,
1224                               (XGI330_SR31 & 0x3F) | 0x40);
1225                 xgifb_reg_set(pVBInfo->P3c4,
1226                               0x32,
1227                               (XGI330_SR32 & 0xFC) | 0x01);
1228         } else {
1229                 xgifb_reg_set(pVBInfo->P3c4, 0x31, XGI330_SR31);
1230                 xgifb_reg_set(pVBInfo->P3c4, 0x32, XGI330_SR32);
1231         }
1232         xgifb_reg_set(pVBInfo->P3c4, 0x33, XGI330_SR33);
1233
1234         if (HwDeviceExtension->jChipType < XG20) {
1235                 if (xgifb_bridge_is_on(pVBInfo)) {
1236                         xgifb_reg_set(pVBInfo->Part2Port, 0x00, 0x1C);
1237                         xgifb_reg_set(pVBInfo->Part4Port,
1238                                       0x0D, XGI330_CRT2Data_4_D);
1239                         xgifb_reg_set(pVBInfo->Part4Port,
1240                                       0x0E, XGI330_CRT2Data_4_E);
1241                         xgifb_reg_set(pVBInfo->Part4Port,
1242                                       0x10, XGI330_CRT2Data_4_10);
1243                         xgifb_reg_set(pVBInfo->Part4Port, 0x0F, 0x3F);
1244                         XGI_LockCRT2(pVBInfo);
1245                 }
1246         } /* != XG20 */
1247
1248         XGI_SenseCRT1(pVBInfo);
1249
1250         if (HwDeviceExtension->jChipType == XG21) {
1251
1252                 xgifb_reg_and_or(pVBInfo->P3d4,
1253                                  0x32,
1254                                  ~Monitor1Sense,
1255                                  Monitor1Sense); /* Z9 default has CRT */
1256                 temp = GetXG21FPBits(pVBInfo);
1257                 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x01, temp);
1258
1259         }
1260         if (HwDeviceExtension->jChipType == XG27) {
1261                 xgifb_reg_and_or(pVBInfo->P3d4,
1262                                  0x32,
1263                                  ~Monitor1Sense,
1264                                  Monitor1Sense); /* Z9 default has CRT */
1265                 temp = GetXG27FPBits(pVBInfo);
1266                 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x03, temp);
1267         }
1268
1269         pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
1270
1271         XGINew_SetDRAMDefaultRegister340(HwDeviceExtension,
1272                                          pVBInfo->P3d4,
1273                                          pVBInfo);
1274
1275         XGINew_SetDRAMSize_340(xgifb_info, HwDeviceExtension, pVBInfo);
1276
1277         xgifb_reg_set(pVBInfo->P3c4, 0x22, 0xfa);
1278         xgifb_reg_set(pVBInfo->P3c4, 0x21, 0xa3);
1279
1280         XGINew_ChkSenseStatus(pVBInfo);
1281         XGINew_SetModeScratch(pVBInfo);
1282
1283         xgifb_reg_set(pVBInfo->P3d4, 0x8c, 0x87);
1284
1285         return 1;
1286 } /* end of init */