1 # SPDX-License-Identifier: GPL-2.0-only
6 select ADD_FSP_BINARIES if USE_AMD_BLOBS
8 select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
9 select CONSOLE_CBMEM_PRINT_PRE_BOOTBLOCK_CONTENTS if VBOOT_STARTS_BEFORE_BOOTBLOCK
10 select DRIVERS_USB_PCI_XHCI
11 select FSP_COMPRESS_FSP_M_LZMA
12 select FSP_COMPRESS_FSP_S_LZMA
13 select GENERIC_GPIO_LIB
14 select HAVE_ACPI_TABLES
16 select HAVE_EM100_SUPPORT
17 select HAVE_SMI_HANDLER
18 select IDT_IN_EVERY_STAGE
19 select PARALLEL_MP_AP_WORK
20 select PLATFORM_USES_FSP2_0
21 select PROVIDES_ROM_SHARING
22 select RESET_VECTOR_IN_RAM
25 select SOC_AMD_COMMON_BLOCK_ACP_GEN1
26 select SOC_AMD_COMMON_BLOCK_ACPI
27 select SOC_AMD_COMMON_BLOCK_ACPIMMIO
28 select SOC_AMD_COMMON_BLOCK_ACPIMMIO_PM_IO_ACCESS
29 select SOC_AMD_COMMON_BLOCK_ACPI_ALIB
30 select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE
31 select SOC_AMD_COMMON_BLOCK_ACPI_GPIO
32 select SOC_AMD_COMMON_BLOCK_ACPI_IVRS
33 select SOC_AMD_COMMON_BLOCK_ACPI_MADT
34 select SOC_AMD_COMMON_BLOCK_AOAC
35 select SOC_AMD_COMMON_BLOCK_APOB
36 select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
37 select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H
38 select SOC_AMD_COMMON_BLOCK_DATA_FABRIC
39 select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN
40 select SOC_AMD_COMMON_BLOCK_EMMC
41 select SOC_AMD_COMMON_BLOCK_EMMC_SKIP_POWEROFF
42 select SOC_AMD_COMMON_BLOCK_GPP_CLK
43 select SOC_AMD_COMMON_BLOCK_GRAPHICS
44 select SOC_AMD_COMMON_BLOCK_HAS_ESPI
45 select SOC_AMD_COMMON_BLOCK_HDA
46 select SOC_AMD_COMMON_BLOCK_I2C
47 select SOC_AMD_COMMON_BLOCK_I2C_PAD_CTRL
48 select SOC_AMD_COMMON_BLOCK_IOMMU
49 select SOC_AMD_COMMON_BLOCK_LPC
50 select SOC_AMD_COMMON_BLOCK_MCAX
51 select SOC_AMD_COMMON_BLOCK_NONCAR
52 select SOC_AMD_COMMON_BLOCK_PCI
53 select SOC_AMD_COMMON_BLOCK_PCIE_GPP_DRIVER
54 select SOC_AMD_COMMON_BLOCK_PM
55 select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE
56 select SOC_AMD_COMMON_BLOCK_PSP_GEN2
57 select SOC_AMD_COMMON_BLOCK_RESET
58 select SOC_AMD_COMMON_BLOCK_SATA
59 select SOC_AMD_COMMON_BLOCK_SMBUS
60 select SOC_AMD_COMMON_BLOCK_SMI
61 select SOC_AMD_COMMON_BLOCK_SMM
62 select SOC_AMD_COMMON_BLOCK_SMU
63 select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY
64 select SOC_AMD_COMMON_BLOCK_SPI
65 select SOC_AMD_COMMON_BLOCK_SVI2
66 select SOC_AMD_COMMON_BLOCK_TSC
67 select SOC_AMD_COMMON_BLOCK_UART
68 select SOC_AMD_COMMON_BLOCK_UCODE
69 select SOC_AMD_COMMON_FSP_DMI_TABLES
70 select SOC_AMD_COMMON_FSP_PCIE_CLK_REQ
71 select SOC_AMD_SUPPORTS_WARM_RESET
73 select UDK_2017_BINDING
75 select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
76 select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
77 select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
78 select X86_AMD_FIXED_MTRRS
79 select X86_INIT_NEED_1_SIPI
80 select HAVE_X86_64_SUPPORT
86 config CHIPSET_DEVICETREE
88 default "soc/amd/picasso/chipset.cb"
91 string "FSP-M (memory init) binary path and filename"
92 depends on ADD_FSP_BINARIES
93 default "3rdparty/amd_blobs/picasso/PICASSO_M.fd"
95 The path and filename of the FSP-M binary for this platform.
98 string "FSP-S (silicon init) binary path and filename"
99 depends on ADD_FSP_BINARIES
100 default "3rdparty/amd_blobs/picasso/PICASSO_S.fd"
102 The path and filename of the FSP-S binary for this platform.
104 config EARLY_RESERVED_DRAM_BASE
108 This variable defines the base address of the DRAM which is reserved
109 for usage by coreboot in early stages (i.e. before ramstage is up).
110 This memory gets reserved in BIOS tables to ensure that the OS does
111 not use it, thus preventing corruption of OS memory in case of S3
114 config EARLYRAM_BSP_STACK_SIZE
118 config PSP_APOB_DRAM_ADDRESS
122 Location in DRAM where the PSP will copy the AGESA PSP Output
125 config PSP_APOB_DRAM_SIZE
129 config PSP_SHAREDMEM_BASE
131 default 0x2011000 if VBOOT
134 This variable defines the base address in DRAM memory where PSP copies
135 the vboot workbuf. This is used in the linker script to have a static
136 allocation for the buffer as well as for adding relevant entries in
137 the BIOS directory table for the PSP.
139 config PSP_SHAREDMEM_SIZE
141 default 0x8000 if VBOOT
144 Sets the maximum size for the PSP to pass the vboot workbuf and
145 any logs or timestamps back to coreboot. This will be copied
146 into main memory by the PSP and will be available when the x86 is
147 started. The workbuf's base depends on the address of the reset
150 config PRE_X86_CBMEM_CONSOLE_SIZE
154 Size of the CBMEM console used in PSP verstage.
156 config PRERAM_CBMEM_CONSOLE_SIZE
160 Increase this value if preram cbmem console is getting truncated
162 config CBFS_MCACHE_SIZE
164 default 0x2000 if VBOOT_STARTS_BEFORE_BOOTBLOCK
166 config C_ENV_BOOTBLOCK_SIZE
170 Sets the size of the bootblock stage that should be loaded in DRAM.
171 This variable controls the DRAM allocation size in linker script
178 Sets the address in DRAM where romstage should be loaded.
184 Sets the size of DRAM allocation for romstage in linker script.
190 Sets the address in DRAM where FSP-M should be loaded. cbfstool
191 performs relocation of FSP-M to this address.
197 Sets the size of DRAM allocation for FSP-M in linker script.
201 depends on VBOOT_SEPARATE_VERSTAGE
204 Sets the address in DRAM where verstage should be loaded if running
205 as a separate stage on x86.
209 depends on VBOOT_SEPARATE_VERSTAGE
212 Sets the size of DRAM allocation for verstage in linker script if
213 running as a separate stage on x86.
215 config ECAM_MMCONF_BASE_ADDRESS
218 config ECAM_MMCONF_BUS_NUMBER
229 Maximum number of threads the platform can have.
235 The default VGA BIOS PCI vendor/device ID should be set to the
236 result of the map_oprom_vendev() function in graphics.c.
240 default "3rdparty/amd_blobs/picasso/PicassoGenericVbios.bin"
242 config VGA_BIOS_SECOND
245 config VGA_BIOS_SECOND_ID
249 Some Dali and all Pollock APUs need a different VBIOS than some other
250 Dali and all Picasso APUs, but don't always have a different PCI
251 vendor/device IDs, so we need an alternate method to determine the
252 correct video BIOS. In map_oprom_vendev(), we look at the return
253 value of soc_is_raven2() and decide which rom to load.
255 config VGA_BIOS_SECOND_FILE
257 default "3rdparty/amd_blobs/picasso/Raven2GenericVbios.bin"
259 config S3_VGA_ROM_RUN
263 config SERIRQ_CONTINUOUS_MODE
267 Set this option to y for serial IRQ in continuous mode.
268 Otherwise it is in quiet mode.
270 config CONSOLE_UART_BASE_ADDRESS
271 depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART
273 default 0xfedc9000 if UART_FOR_CONSOLE = 0
274 default 0xfedca000 if UART_FOR_CONSOLE = 1
275 default 0xfedce000 if UART_FOR_CONSOLE = 2
276 default 0xfedcf000 if UART_FOR_CONSOLE = 3
280 default 0x800000 if HAVE_SMI_HANDLER
283 config SMM_RESERVED_SIZE
287 config SMM_MODULE_STACK_SIZE
292 bool "Build ACPI BERT Table"
294 depends on HAVE_ACPI_TABLES
296 Report Machine Check errors identified in POST to the OS in an
297 ACPI Boot Error Record Table.
299 config ACPI_BERT_SIZE
301 default 0x4000 if ACPI_BERT
304 Specify the amount of DRAM reserved for gathering the data used to
305 generate the ACPI table.
308 select ALWAYS_LOAD_OPROM
309 select ALWAYS_RUN_OPROM
311 config RO_REGION_ONLY
313 depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A
316 config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
320 config DISABLE_SPI_FLASH_ROM_SHARING
323 Instruct the chipset to not honor the EGPIO67_SPI_ROM_REQ pin
324 which indicates a board level ROM transaction request. This
325 removes arbitration with board and assumes the chipset controls
326 the SPI flash bus entirely.
328 config DISABLE_KEYBOARD_RESET_PIN
331 Instruct the SoC to not use the state of GPIO_129 as keyboard reset
332 signal. When this pin is used as GPIO and the keyboard reset
333 functionality isn't disabled, configuring it as an output and driving
334 it as 0 will cause a reset.
336 config FSP_TEMP_RAM_SIZE
340 The amount of coreboot-allocated heap and stack usage by the FSP.
342 menu "PSP Configuration Options"
344 config AMDFW_CONFIG_FILE
346 default "src/soc/amd/picasso/fw.cfg"
348 config PSP_LOAD_MP2_FW
352 Include the MP2 firmwares and configuration into the PSP build.
354 If unsure, answer 'n'
356 config PSP_LOAD_S0I3_FW
360 Select this item to include the S0i3 file into the PSP build.
362 config HAVE_PSP_WHITELIST_FILE
363 bool "Include a debug whitelist file in PSP build"
366 Support secured unlock prior to reset using a whitelisted
367 number? This feature requires a signed whitelist image and
370 If unsure, answer 'n'
372 config PSP_WHITELIST_FILE
373 string "Debug whitelist file path"
374 depends on HAVE_PSP_WHITELIST_FILE
375 default "3rdparty/amd_blobs/picasso/PSP/wtl-rvn.sbin"
377 config PSP_UNLOCK_SECURE_DEBUG
378 bool "Unlock secure debug"
381 Select this item to enable secure debug options in PSP.
383 config PSP_VERSTAGE_FILE
384 string "Specify the PSP_verstage file path"
385 depends on VBOOT_STARTS_BEFORE_BOOTBLOCK
386 default "\$(obj)/psp_verstage.bin"
388 Add psp_verstage file to the build & PSP Directory Table
390 config PSP_VERSTAGE_SIGNING_TOKEN
391 string "Specify the PSP_verstage Signature Token file path"
392 depends on VBOOT_STARTS_BEFORE_BOOTBLOCK
395 Add psp_verstage signature token to the build & PSP Directory Table
397 config PSP_SOFTFUSE_BITS
398 string "PSP Soft Fuse bits to enable"
401 Space separated list of Soft Fuse bits to enable.
402 Bit 0: Enable secure debug (Set by PSP_UNLOCK_SECURE_DEBUG)
403 Bit 15: PSP post code destination: 0=LPC 1=eSPI
404 Bit 29: Disable MP2 firmware loading (Set by PSP_LOAD_MP2_FW)
406 See #55758 (NDA) for additional bit definitions.
411 select VBOOT_VBNV_CMOS
412 select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
414 config VBOOT_STARTS_BEFORE_BOOTBLOCK
417 select ARCH_VERSTAGE_ARMV7
419 Runs verstage on the PSP. Only available on
420 certain ChromeOS branded parts from AMD.
422 config VBOOT_HASH_BLOCK_SIZE
425 depends on VBOOT_STARTS_BEFORE_BOOTBLOCK
427 Because the bulk of the time in psp_verstage to hash the RO cbfs is
428 spent in the overhead of doing svc calls, increasing the hash block
429 size significantly cuts the verstage hashing time as seen below.
435 There's actually still room for an even bigger stack, but we've
436 reached a point of diminishing returns.
438 config CMOS_RECOVERY_BYTE
441 depends on VBOOT_STARTS_BEFORE_BOOTBLOCK
443 If the workbuf is not passed from the PSP to coreboot, set the
444 recovery flag and reboot. The PSP will read this byte, mark the
445 recovery request in VBNV, and reset the system into recovery mode.
447 This is the byte before the default first byte used by VBNV
450 if VBOOT_SLOTS_RW_A && VBOOT_STARTS_BEFORE_BOOTBLOCK
452 config RWA_REGION_ONLY
454 default "apu/amdfw_a"
456 Add a space-delimited list of filenames that should only be in the
459 endif # VBOOT_SLOTS_RW_A && VBOOT_STARTS_BEFORE_BOOTBLOCK
461 if VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK
463 config RWB_REGION_ONLY
465 default "apu/amdfw_b"
467 Add a space-delimited list of filenames that should only be in the
470 endif # VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK
472 endif # SOC_AMD_PICASSO