mb/google/dedede/var/drawcia: Enable LTR mechanism for PCIe root port 8
[coreboot.git] / src / mainboard / asus / p2b / variants / p2b-ls / irq_tables.c
blob1bad19bbfcbf17aab7383fd8e19e5fb50c46403c
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 #include <arch/pirq_routing.h>
5 static const struct irq_routing_table intel_irq_routing_table = {
6 PIRQ_SIGNATURE,
7 PIRQ_VERSION,
8 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
9 0x00, /* Interrupt router bus */
10 (0x04 << 3) | 0x0, /* Interrupt router device */
11 0, /* IRQs devoted exclusively to PCI usage */
12 0x8086, /* Vendor */
13 0x122e, /* Device */
14 0, /* Miniport */
15 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
16 0x10, /* Checksum (has to be set to some value that
17 * would give 0 after the sum of all bytes
18 * for this structure (including checksum).
20 /* clang-format off */
22 /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
23 {0x00, (0x0c << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x1, 0x0},
24 {0x00, (0x0b << 3) | 0x0, {{0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}}, 0x2, 0x0},
25 {0x00, (0x0a << 3) | 0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}}, 0x3, 0x0},
26 {0x00, (0x09 << 3) | 0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}}, 0x4, 0x0},
27 {0x00, (0x04 << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x0, 0x0},
28 {0x00, (0x01 << 3) | 0x0, {{0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}, {0x63, 0x1eb8}}, 0x0, 0x0},
29 {0x00, (0x06 << 3) | 0x0, {{0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}, {0x62, 0x1eb8}}, 0x0, 0x0},
30 {0x00, (0x07 << 3) | 0x0, {{0x62, 0x1eb8}, {0x63, 0x1eb8}, {0x60, 0x1eb8}, {0x61, 0x1eb8}}, 0x0, 0x0},
32 /* clang-format on */
35 unsigned long write_pirq_routing_table(unsigned long addr)
37 return copy_pirq_routing_table(addr, &intel_irq_routing_table);