1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #ifndef _CPU_INTEL_MODEL_206AX_H
4 #define _CPU_INTEL_MODEL_206AX_H
9 /* SandyBridge CPU stepping */
12 #define SNB_STEP_D0 5 /* Also J0 */
14 #define SNB_STEP_D2 7 /* Also J1/Q0 */
16 /* IvyBridge CPU stepping */
25 #define IS_SANDY_CPU(x) ((x & 0xffff0) == 0x206a0)
26 #define IS_SANDY_CPU_C(x) ((x & 0xf) == 4)
27 #define IS_SANDY_CPU_D0(x) ((x & 0xf) == 5)
28 #define IS_SANDY_CPU_D1(x) ((x & 0xf) == 6)
29 #define IS_SANDY_CPU_D2(x) ((x & 0xf) == 7)
31 #define IS_IVY_CPU(x) ((x & 0xffff0) == 0x306a0)
32 #define IS_IVY_CPU_C(x) ((x & 0xf) == 4)
33 #define IS_IVY_CPU_K(x) ((x & 0xf) == 5)
34 #define IS_IVY_CPU_D(x) ((x & 0xf) == 6)
35 #define IS_IVY_CPU_E(x) ((x & 0xf) >= 8)
37 /* SandyBridge/IvyBridge bus clock is fixed at 100MHz */
38 #define SANDYBRIDGE_BCLK 100
40 #define MSR_CORE_THREAD_COUNT 0x35
41 #define MSR_FEATURE_CONFIG 0x13c
42 #define MSR_FLEX_RATIO 0x194
43 #define FLEX_RATIO_LOCK (1 << 20)
44 #define FLEX_RATIO_EN (1 << 16)
45 #define MSR_TEMPERATURE_TARGET 0x1a2
46 #define MSR_LT_LOCK_MEMORY 0x2e7
47 #define MSR_PLATFORM_INFO 0xce
48 #define PLATFORM_INFO_SET_TDP (1 << 29)
50 #define MSR_MISC_PWR_MGMT 0x1aa
51 #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)
52 #define MSR_TURBO_RATIO_LIMIT 0x1ad
53 #define MSR_POWER_CTL 0x1fc
55 #define MSR_PKGC3_IRTL 0x60a
56 #define MSR_PKGC6_IRTL 0x60b
57 #define MSR_PKGC7_IRTL 0x60c
58 #define IRTL_VALID (1 << 15)
59 #define IRTL_1_NS (0 << 10)
60 #define IRTL_32_NS (1 << 10)
61 #define IRTL_1024_NS (2 << 10)
62 #define IRTL_32768_NS (3 << 10)
63 #define IRTL_1048576_NS (4 << 10)
64 #define IRTL_33554432_NS (5 << 10)
65 #define IRTL_RESPONSE_MASK (0x3ff)
67 /* long duration in low dword, short duration in high dword */
68 #define MSR_PKG_POWER_LIMIT 0x610
69 #define PKG_POWER_LIMIT_MASK 0x7fff
70 #define PKG_POWER_LIMIT_EN (1 << 15)
71 #define PKG_POWER_LIMIT_CLAMP (1 << 16)
72 #define PKG_POWER_LIMIT_TIME_SHIFT 17
73 #define PKG_POWER_LIMIT_TIME_MASK 0x7f
75 #define MSR_PP0_CURRENT_CONFIG 0x601
76 #define PP0_CURRENT_LIMIT_LOCK (1U << 31)
77 #define PP0_CURRENT_LIMIT (112 << 3) /* 112 A */
78 #define MSR_PP1_CURRENT_CONFIG 0x602
79 #define PP1_CURRENT_LIMIT_LOCK (1U << 31)
80 #define PP1_CURRENT_LIMIT_SNB (35 << 3) /* 35 A */
81 #define PP1_CURRENT_LIMIT_IVB (50 << 3) /* 50 A */
82 #define MSR_PKG_POWER_SKU_UNIT 0x606
83 #define MSR_PKG_POWER_SKU 0x614
84 #define MSR_PP0_POWER_LIMIT 0x638
85 #define MSR_PP1_POWER_LIMIT 0x640
87 #define IVB_CONFIG_TDP_MIN_CPUID 0x306a2
88 #define MSR_CONFIG_TDP_NOMINAL 0x648
89 #define MSR_CONFIG_TDP_LEVEL1 0x649
90 #define MSR_CONFIG_TDP_LEVEL2 0x64a
91 #define MSR_CONFIG_TDP_CONTROL 0x64b
92 #define MSR_TURBO_ACTIVATION_RATIO 0x64c
94 /* P-state configuration */
95 #define PSS_MAX_ENTRIES 8
96 #define PSS_RATIO_STEP 2
97 #define PSS_LATENCY_TRANSITION 10
98 #define PSS_LATENCY_BUSMASTER 10
100 /* Sanity check config options. */
101 #if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE))
102 # error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + CONFIG_SMM_RESERVED_SIZE)"
104 #if (CONFIG_SMM_TSEG_SIZE < 0x800000)
105 # error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB"
107 #if ((CONFIG_SMM_TSEG_SIZE & (CONFIG_SMM_TSEG_SIZE - 1)) != 0)
108 # error "CONFIG_SMM_TSEG_SIZE is not a power of 2"
110 #if ((CONFIG_IED_REGION_SIZE & (CONFIG_IED_REGION_SIZE - 1)) != 0)
111 # error "CONFIG_IED_REGION_SIZE is not a power of 2"
115 * List of supported C-states for Sandy Bridge/Ivy Bridge.
129 void intel_model_206ax_finalize_smm(void);
131 /* Configure power limits for turbo mode */
132 void set_power_limits(u8 power_limit_1_time
);
133 int cpu_config_tdp_levels(void);
135 static inline u8
cpu_stepping(void)
137 return cpuid_eax(1) & 0xf;