ec/google/chromeec: Optimize battery string readout with caching
[coreboot.git] / src / arch / arm64 / boot.c
blob7a8060fa4927e457c141d942afe280668c31fb76
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <cbmem.h>
4 #include <arch/lib_helpers.h>
5 #include <arch/stages.h>
6 #include <arch/transition.h>
7 #include <bl31.h>
8 #include <program_loading.h>
10 static void run_payload(struct prog *prog)
12 void (*doit)(void *);
13 void *arg;
15 doit = prog_entry(prog);
16 arg = prog_entry_arg(prog);
17 u64 payload_spsr = get_eret_el(EL2, SPSR_USE_L);
19 if (CONFIG(ARM64_USE_ARM_TRUSTED_FIRMWARE))
20 run_bl31((u64)doit, (u64)arg, payload_spsr);
21 else if (CONFIG_ARM64_CURRENT_EL == EL3)
22 transition_to_el2(doit, arg, payload_spsr);
23 else
24 doit(arg);
27 void arch_prog_run(struct prog *prog)
29 void (*doit)(void *);
31 if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) {
32 run_payload(prog);
33 return;
36 doit = prog_entry(prog);
38 doit(prog_entry_arg(prog));
41 /* Generic stage entry point. Can be overridden by board/SoC if needed. */
42 __weak void stage_entry(uintptr_t stage_arg)
44 if (!ENV_ROMSTAGE_OR_BEFORE)
45 _cbmem_top_ptr = stage_arg;
47 main();