2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
5 ## Copyright (C) 2009-2010 coresystems GmbH
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; version 2 of the License.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
17 mainmenu "coreboot configuration"
26 string "Local version string"
28 Append an extra string to the end of the coreboot version.
30 This can be useful if, for instance, you want to append the
31 respective board's hostname or some other identifying string to
32 the coreboot version number, so that you can easily distinguish
33 boot logs of different boards from each other.
36 string "CBFS prefix to use"
39 Select the prefix to all files put into the image. It's "fallback"
40 by default, "normal" is a common alternative.
43 prompt "Compiler to use"
46 This option allows you to select the compiler used for building
48 You must build the coreboot crosscompiler for the board that you
51 To build all the GCC crosscompilers (takes a LONG time), run:
54 For help on individual architectures, run the command:
60 Use the GNU Compiler Collection (GCC) to build coreboot.
62 For details see http://gcc.gnu.org.
64 config COMPILER_LLVM_CLANG
65 bool "LLVM/clang (TESTING ONLY - Not currently working)"
67 Use LLVM/clang to build coreboot. To use this, you must build the
68 coreboot version of the clang compiler. Run the command
70 Note that this option is not currently working correctly and should
71 really only be selected if you're trying to work on getting clang
74 For details see http://clang.llvm.org.
79 bool "Allow building with any toolchain"
82 Many toolchains break when building coreboot since it uses quite
83 unusual linker features. Unless developers explicitely request it,
84 we'll have to assume that they use their distro compiler by mistake.
85 Make sure that using patched compilers is a conscious decision.
88 bool "Use ccache to speed up (re)compilation"
91 Enables the use of ccache for faster builds.
93 Requires the ccache utility in your system $PATH.
95 For details see https://ccache.samba.org.
98 bool "Generate flashmap descriptor parser using flex and bison"
101 Enable this option if you are working on the flashmap descriptor
102 parser and made changes to fmd_scanner.l or fmd_parser.y.
104 Otherwise, say N to use the provided pregenerated scanner/parser.
106 config UTIL_GENPARSER
107 bool "Generate SCONFIG & BINCFG parser using flex and bison"
110 Enable this option if you are working on the sconfig device tree
111 parser or bincfg and made changes to the .l or .y files.
113 Otherwise, say N to use the provided pregenerated scanner/parser.
115 config USE_OPTION_TABLE
116 bool "Use CMOS for configuration values"
117 depends on HAVE_OPTION_TABLE
119 Enable this option if coreboot shall read options from the "CMOS"
120 NVRAM instead of using hard-coded values.
122 config STATIC_OPTION_TABLE
123 bool "Load default configuration values into CMOS on each boot"
124 depends on USE_OPTION_TABLE
126 Enable this option to reset "CMOS" NVRAM values to default on
127 every boot. Use this if you want the NVRAM configuration to
128 never be modified from its default values.
130 config COMPRESS_RAMSTAGE
131 bool "Compress ramstage with LZMA"
132 # Default value set at the end of the file
134 Compress ramstage to save memory in the flash image. Note
135 that decompression might slow down booting if the boot flash
136 is connected through a slow link (i.e. SPI).
138 config COMPRESS_PRERAM_STAGES
139 bool "Compress romstage and verstage with LZ4"
141 # Default value set at the end of the file
143 Compress romstage and (if it exists) verstage with LZ4 to save flash
144 space and speed up boot, since the time for reading the image from SPI
145 (and in the vboot case verifying it) is usually much greater than the
146 time spent decompressing. Doesn't work for XIP stages (assume all
147 ARCH_X86 for now) for obvious reasons.
149 config COMPRESS_BOOTBLOCK
152 This option can be used to compress the bootblock with LZ4 and attach
153 a small self-decompression stub to its front. This can drastically
154 reduce boot time on platforms where the bootblock is loaded over a
155 very slow connection and bootblock size trumps all other factors for
156 speed. Since using this option usually requires changes to the
157 SoC memlayout and possibly extra support code, it should not be
158 user-selectable. (There's no real point in offering this to the user
159 anyway... if it works and saves boot time, you would always want it.)
161 config INCLUDE_CONFIG_FILE
162 bool "Include the coreboot .config file into the ROM image"
163 # Default value set at the end of the file
165 Include the .config file that was used to compile coreboot
166 in the (CBFS) ROM image. This is useful if you want to know which
167 options were used to build a specific coreboot.rom image.
169 Saying Y here will increase the image size by 2-3KB.
171 You can use the following command to easily list the options:
173 grep -a CONFIG_ coreboot.rom
175 Alternatively, you can also use cbfstool to print the image
176 contents (including the raw 'config' item we're looking for).
180 $ cbfstool coreboot.rom print
181 coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
185 Name Offset Type Size
186 cmos_layout.bin 0x0 cmos layout 1159
187 fallback/romstage 0x4c0 stage 339756
188 fallback/ramstage 0x53440 stage 186664
189 fallback/payload 0x80dc0 payload 51526
190 config 0x8d740 raw 3324
191 (empty) 0x8e480 null 3610440
193 config COLLECT_TIMESTAMPS
194 bool "Create a table of timestamps collected during boot"
195 default y if ARCH_X86
197 Make coreboot create a table of timer-ID/timer-value pairs to
198 allow measuring time spent at different phases of the boot process.
200 config TIMESTAMPS_ON_CONSOLE
201 bool "Print the timestamp values on the console"
203 depends on COLLECT_TIMESTAMPS
205 Print the timestamps to the debug console if enabled at level spew.
208 bool "Allow use of binary-only repository"
210 This draws in the blobs repository, which contains binary files that
211 might be required for some chipsets or boards.
212 This flag ensures that a "Free" option remains available for users.
215 bool "Code coverage support"
216 depends on COMPILER_GCC
218 Add code coverage support for coreboot. This will store code
219 coverage information in CBMEM for extraction from user space.
223 bool "Undefined behavior sanitizer support"
226 Instrument the code with checks for undefined behavior. If unsure,
227 say N because it adds a small performance penalty and may abort
228 on code that happens to work in spite of the UB.
230 config NO_RELOCATABLE_RAMSTAGE
232 default n if ARCH_X86
235 config RELOCATABLE_RAMSTAGE
237 default !NO_RELOCATABLE_RAMSTAGE
238 select RELOCATABLE_MODULES
240 The reloctable ramstage support allows for the ramstage to be built
241 as a relocatable module. The stage loader can identify a place
242 out of the OS way so that copying memory is unnecessary during an S3
243 wake. When selecting this option the romstage is responsible for
244 determing a stack location to use for loading the ramstage.
246 config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
247 depends on RELOCATABLE_RAMSTAGE
250 The relocated ramstage is saved in an area specified by the
251 by the board and/or chipset.
254 bool "Update existing coreboot.rom image"
256 If this option is enabled, no new coreboot.rom file
257 is created. Instead it is expected that there already
258 is a suitable file for further processing.
259 The bootblock will not be modified.
261 If unsure, select 'N'
263 config BOOTSPLASH_IMAGE
264 bool "Add a bootsplash image"
266 Select this option if you have a bootsplash image that you would
267 like to add to your ROM.
269 This will only add the image to the ROM. To actually run it check
270 options under 'Display' section.
272 config BOOTSPLASH_FILE
273 string "Bootsplash path and filename"
274 depends on BOOTSPLASH_IMAGE
275 # Default value set at the end of the file
277 The path and filename of the file to use as graphical bootsplash
278 screen. The file format has to be jpg.
284 source "src/mainboard/Kconfig"
288 default "devicetree.cb"
290 This symbol allows mainboards to select a different file under their
291 mainboard directory for the devicetree.cb file. This allows the board
292 variants that need different devicetrees to be in the same directory.
294 Examples: "devicetree.variant.cb"
295 "variant/devicetree.cb"
297 config OVERRIDE_DEVICETREE
301 This symbol allows variants to provide an override devicetree file to
302 override the registers and/or add new devices on top of the ones
303 provided by baseboard devicetree using CONFIG_DEVICETREE.
305 Examples: "devicetree.variant-override.cb"
306 "variant/devicetree-override.cb"
309 hex "Size of CBFS filesystem in ROM"
310 # Default value set at the end of the file
312 This is the part of the ROM actually managed by CBFS, located at the
313 end of the ROM (passed through cbfstool -o) on x86 and at at the start
314 of the ROM (passed through cbfstool -s) everywhere else. It defaults
315 to span the whole ROM on all but Intel systems that use an Intel Firmware
316 Descriptor. It can be overridden to make coreboot live alongside other
317 components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE
321 string "fmap description file in fmd format"
322 default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS
325 The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
326 but in some cases more complex setups are required.
327 When an fmd is specified, it overrides the default format.
331 # load site-local kconfig to allow user specific defaults and overrides
332 source "site-local/Kconfig"
334 config SYSTEM_TYPE_LAPTOP
338 config SYSTEM_TYPE_TABLET
342 config SYSTEM_TYPE_DETACHABLE
346 config SYSTEM_TYPE_CONVERTIBLE
350 config CBFS_AUTOGEN_ATTRIBUTES
354 If this option is selected, every file in cbfs which has a constraint
355 regarding position or alignment will get an additional file attribute
356 which describes this constraint.
361 source "src/soc/*/Kconfig"
363 source "src/cpu/Kconfig"
364 comment "Northbridge"
365 source "src/northbridge/*/*/Kconfig"
366 comment "Southbridge"
367 source "src/southbridge/*/*/Kconfig"
369 source "src/superio/*/*/Kconfig"
370 comment "Embedded Controllers"
371 source "src/ec/acpi/Kconfig"
372 source "src/ec/*/*/Kconfig"
373 # FIXME move to vendorcode
374 source "src/drivers/intel/fsp1_0/Kconfig"
376 source "src/southbridge/intel/common/firmware/Kconfig"
377 source "src/vendorcode/*/Kconfig"
379 source "src/arch/*/Kconfig"
383 source "src/device/Kconfig"
385 menu "Generic Drivers"
386 source "src/drivers/*/Kconfig"
387 source "src/drivers/*/*/Kconfig"
388 source "src/commonlib/storage/Kconfig"
393 source "src/security/Kconfig"
397 source "src/acpi/Kconfig"
399 # This option is for the current boards/chipsets where SPI flash
400 # is not the boot device. Currently nearly all boards/chipsets assume
401 # SPI flash is the boot device.
402 config BOOT_DEVICE_NOT_SPI_FLASH
406 config BOOT_DEVICE_SPI_FLASH
408 default y if !BOOT_DEVICE_NOT_SPI_FLASH
411 config BOOT_DEVICE_MEMORY_MAPPED
413 default y if ARCH_X86 && BOOT_DEVICE_SPI_FLASH
416 Inform system if SPI is memory-mapped or not.
418 config BOOT_DEVICE_SUPPORTS_WRITES
422 Indicate that the platform has writable boot device
435 default 0x1000 if ARCH_X86
442 source "src/console/Kconfig"
444 config HAVE_ACPI_RESUME
448 config ACPI_HUGE_LOWMEM_BACKUP
452 On S3 resume path, backup low memory from RAMBASE..RAMTOP in CBMEM.
454 config RESUME_PATH_SAME_AS_BOOT
456 default y if ARCH_X86
457 depends on HAVE_ACPI_RESUME
459 This option indicates that when a system resumes it takes the
460 same path as a regular boot. e.g. an x86 system runs from the
461 reset vector at 0xfffffff0 on both resume and warm/cold boot.
463 config HAVE_ROMSTAGE_CONSOLE_SPINLOCK
467 config HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK
471 This should be enabled on certain plaforms, such as the AMD
472 SR565x, that cannot handle concurrent CBFS accesses from
473 multiple APs during early startup.
475 config HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK
479 config HAVE_MONOTONIC_TIMER
482 The board/chipset provides a monotonic timer.
484 config GENERIC_UDELAY
486 depends on HAVE_MONOTONIC_TIMER
488 The board/chipset uses a generic udelay function utilizing the
493 depends on HAVE_MONOTONIC_TIMER
495 Provide a timer queue for performing time-based callbacks.
497 config COOP_MULTITASKING
499 depends on TIMER_QUEUE && ARCH_X86
501 Cooperative multitasking allows callbacks to be multiplexed on the
502 main thread of ramstage. With this enabled it allows for multiple
503 execution paths to take place when they have udelay() calls within
509 depends on COOP_MULTITASKING
511 How many execution threads to cooperatively multitask with.
513 config HAVE_OPTION_TABLE
517 This variable specifies whether a given board has a cmos.layout
518 file containing NVRAM/CMOS bit definitions.
519 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
525 config HAVE_SMI_HANDLER
529 config PCI_IO_CFG_EXT
537 config USE_WATCHDOG_ON_BOOT
545 Enable Unified Memory Architecture for graphics.
547 config HAVE_ACPI_TABLES
550 This variable specifies whether a given board has ACPI table support.
551 It is usually set in mainboard/*/Kconfig.
556 This variable specifies whether a given board has MP table support.
557 It is usually set in mainboard/*/Kconfig.
558 Whether or not the MP table is actually generated by coreboot
559 is configurable by the user via GENERATE_MP_TABLE.
561 config HAVE_PIRQ_TABLE
564 This variable specifies whether a given board has PIRQ table support.
565 It is usually set in mainboard/*/Kconfig.
566 Whether or not the PIRQ table is actually generated by coreboot
567 is configurable by the user via GENERATE_PIRQ_TABLE.
569 config MAX_PIRQ_LINKS
573 This variable specifies the number of PIRQ interrupt links which are
574 routable. On most chipsets, this is 4, INTA through INTD. Some
575 chipsets offer more than four links, commonly up to INTH. They may
576 also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
577 table specifies links greater than 4, pirq_route_irqs will not
578 function properly, unless this variable is correctly set.
588 Build support for NHLT (non HD Audio) ACPI table generation.
592 depends on HAVE_ACPI_TABLES
594 Build an ACPI Boot Error Record Table.
596 #These Options are here to avoid "undefined" warnings.
597 #The actual selection and help texts are in the following menu.
601 config GENERATE_MP_TABLE
602 prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
604 default HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
606 Generate an MP table (conforming to the Intel MultiProcessor
607 specification 1.4) for this board.
611 config GENERATE_PIRQ_TABLE
612 prompt "Generate a PIRQ table" if HAVE_PIRQ_TABLE
614 default HAVE_PIRQ_TABLE
616 Generate a PIRQ table for this board.
620 config GENERATE_SMBIOS_TABLES
622 bool "Generate SMBIOS tables"
625 Generate SMBIOS tables for this board.
629 config SMBIOS_PROVIDED_BY_MOBO
633 config MAINBOARD_SERIAL_NUMBER
634 prompt "SMBIOS Serial Number" if !SMBIOS_PROVIDED_BY_MOBO
636 depends on GENERATE_SMBIOS_TABLES
639 The Serial Number to store in SMBIOS structures.
641 config MAINBOARD_VERSION
642 prompt "SMBIOS Version Number" if !SMBIOS_PROVIDED_BY_MOBO
644 depends on GENERATE_SMBIOS_TABLES
647 The Version Number to store in SMBIOS structures.
649 config MAINBOARD_SMBIOS_MANUFACTURER
650 prompt "SMBIOS Manufacturer" if !SMBIOS_PROVIDED_BY_MOBO
652 depends on GENERATE_SMBIOS_TABLES
653 default MAINBOARD_VENDOR
655 Override the default Manufacturer stored in SMBIOS structures.
657 config MAINBOARD_SMBIOS_PRODUCT_NAME
658 prompt "SMBIOS Product name" if !SMBIOS_PROVIDED_BY_MOBO
660 depends on GENERATE_SMBIOS_TABLES
661 default MAINBOARD_PART_NUMBER
663 Override the default Product name stored in SMBIOS structures.
665 config SMBIOS_ENCLOSURE_TYPE
667 depends on GENERATE_SMBIOS_TABLES
668 default 0x09 if SYSTEM_TYPE_LAPTOP
669 default 0x1e if SYSTEM_TYPE_TABLET
670 default 0x1f if SYSTEM_TYPE_CONVERTIBLE
671 default 0x20 if SYSTEM_TYPE_DETACHABLE
674 System Enclosure or Chassis Types as defined in SMBIOS specification.
675 The default value is SMBIOS_ENCLOSURE_DESKTOP (0x03) but laptop,
676 convertible, or tablet enclosure will be used if the appropriate
677 system type is selected.
681 source "payloads/Kconfig"
685 comment "CPU Debug Settings"
686 source "src/cpu/*/Kconfig.debug"
688 comment "General Debug Settings"
690 # TODO: Better help text and detailed instructions.
692 bool "GDB debugging support"
694 depends on CONSOLE_SERIAL
696 If enabled, you will be able to set breakpoints for gdb debugging.
697 See src/arch/x86/lib/c_start.S for details.
700 bool "Wait for a GDB connection in the ramstage"
704 If enabled, coreboot will wait for a GDB connection in the ramstage.
708 bool "Halt when hitting a BUG() or assertion error"
711 If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().
713 config HAVE_DEBUG_GPIO
717 bool "Output verbose GPIO debug messages"
718 depends on HAVE_DEBUG_GPIO
721 bool "Output verbose CBFS debug messages"
724 This option enables additional CBFS related debug messages.
726 config HAVE_DEBUG_RAM_SETUP
729 config DEBUG_RAM_SETUP
730 bool "Output verbose RAM init debug messages"
732 depends on HAVE_DEBUG_RAM_SETUP
734 This option enables additional RAM init related debug messages.
735 It is recommended to enable this when debugging issues on your
736 board which might be RAM init related.
738 Note: This option will increase the size of the coreboot image.
743 bool "Check PIRQ table consistency"
745 depends on GENERATE_PIRQ_TABLE
749 config HAVE_DEBUG_SMBUS
753 bool "Output verbose SMBus debug messages"
755 depends on HAVE_DEBUG_SMBUS
757 This option enables additional SMBus (and SPD) debug messages.
759 Note: This option will increase the size of the coreboot image.
764 bool "Output verbose SMI debug messages"
766 depends on HAVE_SMI_HANDLER
767 select SPI_FLASH_SMM if SPI_CONSOLE || CONSOLE_SPI_FLASH
769 This option enables additional SMI related debug messages.
771 Note: This option will increase the size of the coreboot image.
775 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
776 # printk(BIOS_DEBUG, ...) calls.
778 prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
782 This option enables additional malloc related debug messages.
784 Note: This option will increase the size of the coreboot image.
788 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
789 # printk(BIOS_DEBUG, ...) calls.
791 prompt "Output verbose ACPI debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
795 This option enables additional ACPI related debug messages.
797 Note: This option will slightly increase the size of the coreboot image.
801 config DEBUG_CONSOLE_INIT
802 bool "Debug console initialisation code"
805 With this option printk()'s are attempted before console hardware
806 initialisation has been completed. Your mileage may vary.
808 Typically you will need to modify source in console_hw_init() such
809 that a working console appears before the one you want to debug.
813 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
814 # printk(BIOS_DEBUG, ...) calls.
815 config REALMODE_DEBUG
816 prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
819 depends on PCI_OPTION_ROM_RUN_REALMODE
821 This option enables additional x86emu related debug messages.
823 Note: This option will increase the time to emulate a ROM.
828 bool "Output verbose x86emu debug messages"
830 depends on PCI_OPTION_ROM_RUN_YABEL
832 This option enables additional x86emu related debug messages.
834 Note: This option will increase the size of the coreboot image.
838 config X86EMU_DEBUG_JMP
839 bool "Trace JMP/RETF"
841 depends on X86EMU_DEBUG
843 Print information about JMP and RETF opcodes from x86emu.
845 Note: This option will increase the size of the coreboot image.
849 config X86EMU_DEBUG_TRACE
850 bool "Trace all opcodes"
852 depends on X86EMU_DEBUG
854 Print _all_ opcodes that are executed by x86emu.
856 WARNING: This will produce a LOT of output and take a long time.
858 Note: This option will increase the size of the coreboot image.
862 config X86EMU_DEBUG_PNP
863 bool "Log Plug&Play accesses"
865 depends on X86EMU_DEBUG
867 Print Plug And Play accesses made by option ROMs.
869 Note: This option will increase the size of the coreboot image.
873 config X86EMU_DEBUG_DISK
876 depends on X86EMU_DEBUG
878 Print Disk I/O related messages.
880 Note: This option will increase the size of the coreboot image.
884 config X86EMU_DEBUG_PMM
887 depends on X86EMU_DEBUG
889 Print messages related to POST Memory Manager (PMM).
891 Note: This option will increase the size of the coreboot image.
896 config X86EMU_DEBUG_VBE
897 bool "Debug VESA BIOS Extensions"
899 depends on X86EMU_DEBUG
901 Print messages related to VESA BIOS Extension (VBE) functions.
903 Note: This option will increase the size of the coreboot image.
907 config X86EMU_DEBUG_INT10
908 bool "Redirect INT10 output to console"
910 depends on X86EMU_DEBUG
912 Let INT10 (i.e. character output) calls print messages to debug output.
914 Note: This option will increase the size of the coreboot image.
918 config X86EMU_DEBUG_INTERRUPTS
919 bool "Log intXX calls"
921 depends on X86EMU_DEBUG
923 Print messages related to interrupt handling.
925 Note: This option will increase the size of the coreboot image.
929 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
930 bool "Log special memory accesses"
932 depends on X86EMU_DEBUG
934 Print messages related to accesses to certain areas of the virtual
935 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
937 Note: This option will increase the size of the coreboot image.
941 config X86EMU_DEBUG_MEM
942 bool "Log all memory accesses"
944 depends on X86EMU_DEBUG
946 Print memory accesses made by option ROM.
947 Note: This also includes accesses to fetch instructions.
949 Note: This option will increase the size of the coreboot image.
953 config X86EMU_DEBUG_IO
954 bool "Log IO accesses"
956 depends on X86EMU_DEBUG
958 Print I/O accesses made by option ROM.
960 Note: This option will increase the size of the coreboot image.
964 config X86EMU_DEBUG_TIMINGS
965 bool "Output timing information"
967 depends on X86EMU_DEBUG && UDELAY_LAPIC && HAVE_MONOTONIC_TIMER
969 Print timing information needed by i915tool.
973 config DEBUG_SPI_FLASH
974 bool "Output verbose SPI flash debug messages"
978 This option enables additional SPI flash related debug messages.
980 if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8
981 # Only visible with the right southbridge and loglevel.
982 config DEBUG_INTEL_ME
983 bool "Verbose logging for Intel Management Engine"
986 Enable verbose logging for Intel Management Engine driver that
987 is present on Intel 6-series chipsets.
991 bool "Trace function calls"
994 If enabled, every function will print information to console once
995 the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
996 the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
997 of calling function. Please note some printk related functions
998 are omitted from trace to have good looking console dumps.
1000 config DEBUG_COVERAGE
1001 bool "Debug code coverage"
1005 If enabled, the code coverage hooks in coreboot will output some
1006 information about the coverage data that is dumped.
1008 config DEBUG_BOOT_STATE
1009 bool "Debug boot state machine"
1012 Control debugging of the boot state machine. When selected displays
1013 the state boundaries in ramstage.
1015 config DEBUG_ADA_CODE
1016 bool "Compile debug code in Ada sources"
1019 Add the compiler switch `-gnata` to compile code guarded by
1022 config HAVE_EM100_SUPPORT
1023 bool "Platform can support the Dediprog EM100 SPI emulator"
1025 This is enabled by platforms which can support using the EM100.
1028 bool "Configure image for EM100 usage"
1029 depends on HAVE_EM100_SUPPORT
1031 The Dediprog EM100 SPI emulator allows fast loading of new SPI images
1032 over USB. However it only supports a maximum SPI clock of 20MHz and
1033 single data output. Enable this option to use a 20MHz SPI clock and
1034 disable "Dual Output Fast Read" Support.
1036 On AMD platforms this changes the SPI speed at run-time if the
1037 mainboard code supports this. On supported Intel platforms this works
1038 by changing the settings in the descriptor.bin file.
1043 ###############################################################################
1044 # Set variables with no prompt - these can be set anywhere, and putting at
1045 # the end of this file gives the most flexibility.
1047 source "src/lib/Kconfig"
1049 config ENABLE_APIC_EXT_ID
1053 config WARNINGS_ARE_ERRORS
1057 # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
1058 # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
1059 # mutually exclusive. One of these options must be selected in the
1060 # mainboard Kconfig if the chipset supports enabling and disabling of
1061 # the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
1062 # in mainboard/Kconfig to know if the button should be enabled or not.
1064 config POWER_BUTTON_DEFAULT_ENABLE
1067 Select when the board has a power button which can optionally be
1068 disabled by the user.
1070 config POWER_BUTTON_DEFAULT_DISABLE
1073 Select when the board has a power button which can optionally be
1074 enabled by the user, e.g. when the board ships with a jumper over
1075 the power switch contacts.
1077 config POWER_BUTTON_FORCE_ENABLE
1080 Select when the board requires that the power button is always
1083 config POWER_BUTTON_FORCE_DISABLE
1086 Select when the board requires that the power button is always
1087 disabled, e.g. when it has been hardwired to ground.
1089 config POWER_BUTTON_IS_OPTIONAL
1091 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
1092 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
1094 Internal option that controls ENABLE_POWER_BUTTON visibility.
1100 Internal option that controls whether we compile in register scripts.
1102 config MAX_REBOOT_CNT
1106 Internal option that sets the maximum number of bootblock executions allowed
1107 with the normal image enabled before assuming the normal image is defective
1108 and switching to the fallback image.
1110 config UNCOMPRESSED_RAMSTAGE
1113 config NO_XIP_EARLY_STAGES
1115 default n if ARCH_X86
1118 Identify if early stages are eXecute-In-Place(XIP).
1120 config EARLY_CBMEM_LIST
1124 Enable display of CBMEM during romstage and postcar.
1126 config RELOCATABLE_MODULES
1129 If RELOCATABLE_MODULES is selected then support is enabled for
1130 building relocatable modules in the RAM stage. Those modules can be
1131 loaded anywhere and all the relocations are handled automatically.
1133 config NO_STAGE_CACHE
1135 default y if !HAVE_ACPI_RESUME
1137 Do not save any component in stage cache for resume path. On resume,
1138 all components would be read back from CBFS again.
1140 config GENERIC_GPIO_LIB
1143 If enabled, compile the generic GPIO library. A "generic" GPIO
1144 implies configurability usually found on SoCs, particularly the
1145 ability to control internal pull resistors.
1147 config GENERIC_SPD_BIN
1150 If enabled, add support for adding spd.hex files in cbfs as spd.bin
1151 and locating it runtime to load SPD. Additionally provide provision to
1152 fetch SPD over SMBus.
1157 depends on GENERIC_SPD_BIN
1159 Total number of memory DIMM slots available on motherboard.
1160 It is multiplication of number of channel to number of DIMMs per
1163 config DIMM_SPD_SIZE
1167 Total SPD size that will be used for DIMM.
1168 Ex: DDR3 256, DDR4 512.
1170 config SPD_READ_BY_WORD
1173 config BOOTBLOCK_CUSTOM
1174 # To be selected by arch, SoC or mainboard if it does not want use the normal
1175 # src/lib/bootblock.c#main() C entry point.
1178 config C_ENVIRONMENT_BOOTBLOCK
1179 # To be selected by arch or platform if a C environment is available during the
1180 # bootblock. Normally this signifies availability of RW memory (e.g. SRAM).
1183 ###############################################################################
1184 # Set default values for symbols created before mainboards. This allows the
1185 # option to be displayed in the general menu, but the default to be loaded in
1186 # the mainboard if desired.
1187 config COMPRESS_RAMSTAGE
1188 default y if !UNCOMPRESSED_RAMSTAGE
1190 config COMPRESS_PRERAM_STAGES
1191 depends on !ARCH_X86
1194 config INCLUDE_CONFIG_FILE
1197 config BOOTSPLASH_FILE
1198 depends on BOOTSPLASH_IMAGE
1199 default "bootsplash.jpg"