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mb/google/brya: Add custom PLD fields to devicetree for brya variants
[coreboot.git] / src / mainboard / google / brya / variants / primus4es / overridetree.cb
blobd4f72374238921a5a949ed44524393c7d4d0693a
1 fw_config
2 field DB_USB 0 3
3 option USB_ABSENT 0
4 option USB3_PS8811 1
5 end
6 field DB_SD 4 5
7 option SD_ABSENT 0
8 option SD_GL9755S 1
9 end
10 field KB_BL 7 7
11 option KB_BL_ABSENT 0
12 option KB_BL_PRESENT 1
13 end
14 field AUDIO 8 10
15 option AUDIO_UNKNOWN 0
16 option MAX98360_ALC5682I_I2S 1
17 option MAX98360_ALC5682I_VS_I2S 2
18 end
19 field DB_LTE 11 12
20 option LTE_ABSENT 0
21 option LTE_USB 1
22 end
23 end
24
25 chip soc/intel/alderlake
26 register "SaGv" = "SaGv_Enabled"
27 register "MaxDramSpeed" = "3733"
28 # Acoustic settings
29 register "AcousticNoiseMitigation" = "1"
30 register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8"
31 register "SlowSlewRate[VR_DOMAIN_GT]" = "SLEW_FAST_8"
32 register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1"
33 register "FastPkgCRampDisable[VR_DOMAIN_GT]" = "1"
34
35 # Intel Common SoC Config
36 #+-------------------+---------------------------+
37 #| Field | Value |
38 #+-------------------+---------------------------+
39 #| GSPI1 | Fingerprint MCU |
40 #| I2C0 | Audio |
41 #| I2C1 | Touchscreen |
42 #| I2C2 | |
43 #| I2C3 | cr50 TPM. Early init is |
44 #| | required to set up a BAR |
45 #| | for TPM communication |
46 #| I2C5 | Trackpad |
47 #+-------------------+---------------------------+
48 register "common_soc_config" = "{
49 .i2c[0] = {
50 .speed = I2C_SPEED_FAST,
51 },
52 .i2c[1] = {
53 .speed = I2C_SPEED_FAST,
54 },
55 .i2c[2] = {
56 .speed = I2C_SPEED_FAST,
57 },
58 .i2c[3] = {
59 .early_init = 1,
60 .speed = I2C_SPEED_FAST,
61 },
62 .i2c[5] = {
63 .speed = I2C_SPEED_FAST,
64 },
65 }"
66
67 register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2_C1
68 register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port
69 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port
70 register "usb3_ports[2]" = "USB3_PORT_EMPTY"
71 register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"
72
73 device domain 0 on
74 device ref dtt on
75 chip drivers/intel/dptf
76 ## sensor information
77 register "options.tsr[0].desc" = ""CPU""
78 register "options.tsr[1].desc" = ""SSD""
79 register "options.tsr[2].desc" = ""CHARGER""
80 register "options.tsr[3].desc" = ""MEMORY""
81 register "options.tsr[4].desc" = ""TYPEC""
82 # TODO: below values are initial reference values only
83
84 ## Passive Policy
85 register "policies.passive" = "{
86 [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
87 [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 90, 5000),
88 [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 92, 5000),
89 [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 90, 5000),
90 [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 90, 5000),
91 [5] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_4, 90, 5000),
92
93 }"
94
95 ## Critical Policy
96 register "policies.critical" = "{
97 [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
98 [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
99 [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 89, SHUTDOWN),
100 [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
101 [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 85, SHUTDOWN),
102 [5] = DPTF_CRITICAL(TEMP_SENSOR_4, 85, SHUTDOWN),
103 }"
104
105 register "controls.power_limits" = "{
106 .pl1 = {
107 .min_power = 3000,
108 .max_power = 15000,
109 .time_window_min = 28 * MSECS_PER_SEC,
110 .time_window_max = 32 * MSECS_PER_SEC,
111 .granularity = 250,
112 },
113 .pl2 = {
114 .min_power = 55000,
115 .max_power = 55000,
116 .time_window_min = 28 * MSECS_PER_SEC,
117 .time_window_max = 32 * MSECS_PER_SEC,
118 .granularity = 1000,
119 }
120 }"
121
122 ## Charger Performance Control (Control, mA)
123 register "controls.charger_perf" = "{
124 [0] = { 255, 1700 },
125 [1] = { 24, 1500 },
126 [2] = { 16, 1000 },
127 [3] = { 8, 500 }
128 }"
129 device generic 0 alias dptf_policy on end
130 end
131 end
132 device ref cnvi_wifi on
133 chip drivers/wifi/generic
134 register "wake" = "GPE0_PME_B0"
135 device generic 0 on end
136 end
137 end
138 device ref pcie_rp3 on
139 chip soc/intel/common/block/pcie/rtd3
140 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)"
141 register "srcclk_pin" = "6"
142 device generic 0 alias emmc_rtd3 on end
143 end
144 # Enable PCIe-to-eMMC bridge PCIE 3 using clk 6
145 register "pch_pcie_rp[PCH_RP(3)]" = "{
146 .clk_src = 6,
147 .clk_req = 6,
148 .flags = PCIE_RP_LTR | PCIE_RP_AER,
149 }"
150 end #PCIE3 BH799BB
151 device ref tcss_dma0 on
152 chip drivers/intel/usb4/retimer
153 register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
154 use tcss_usb3_port1 as dfp[0].typec_port
155 device generic 0 on end
156 end
157 end
158 device ref tcss_dma1 on
159 chip drivers/intel/usb4/retimer
160 register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
161 use tcss_usb3_port3 as dfp[0].typec_port
162 device generic 0 on end
163 end
164 end
165 device ref pcie_rp6 off end #PCIE6 WWAN
166 device ref pcie_rp8 on
167 chip soc/intel/common/block/pcie/rtd3
168 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
169 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)"
170 register "srcclk_pin" = "3"
171 device generic 0 on end
172 end
173 end #PCIE8 SD card
174 device ref pcie_rp9 on
175 # Enable NVMe PCIE 9 using clk 0
176 register "pch_pcie_rp[PCH_RP(9)]" = "{
177 .clk_src = 0,
178 .clk_req = 0,
179 .flags = PCIE_RP_LTR | PCIE_RP_AER,
180 }"
181 end #PCIE9-12 SSD
182 device ref i2c0 on
183 chip drivers/i2c/generic
184 register "hid" = ""10EC5682""
185 register "name" = ""RT58""
186 register "desc" = ""Headset Codec""
187 register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)"
188 # Set the jd_src to RT5668_JD1 for jack detection
189 register "property_count" = "1"
190 register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
191 register "property_list[0].name" = ""realtek,jd-src""
192 register "property_list[0].integer" = "1"
193 device i2c 1a alias audio_codec on
194 probe AUDIO MAX98360_ALC5682I_I2S
195 probe AUDIO MAX98360_ALC5682I_VS_I2S
196 end
197 end
198 end #I2C0
199 device ref i2c1 on
200 chip drivers/i2c/hid
201 register "generic.hid" = ""ELAN9050""
202 register "generic.desc" = ""ELAN Touchscreen""
203 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
204 register "generic.probed" = "1"
205 register "generic.reset_gpio" =
206 "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
207 register "generic.reset_delay_ms" = "300"
208 register "generic.reset_off_delay_ms" = "1"
209 register "generic.enable_gpio" =
210 "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
211 register "generic.enable_delay_ms" = "6"
212 register "generic.stop_gpio" =
213 "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
214 register "generic.stop_off_delay_ms" = "1"
215 register "generic.has_power_resource" = "1"
216 register "generic.disable_gpio_export_in_crs" = "1"
217 register "hid_desc_reg_offset" = "0x01"
218 device i2c 0x10 on end
219 end
220 chip drivers/i2c/hid
221 register "generic.hid" = ""GTCH7503""
222 register "generic.desc" = ""G2TOUCH Touchscreen""
223 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
224 register "generic.probed" = "1"
225 register "generic.reset_gpio" =
226 "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
227 register "generic.reset_delay_ms" = "50"
228 register "generic.enable_gpio" =
229 "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
230 register "generic.enable_delay_ms" = "1"
231 register "generic.has_power_resource" = "1"
232 register "generic.disable_gpio_export_in_crs" = "1"
233 register "hid_desc_reg_offset" = "0x01"
234 device i2c 0x40 on end
235 end
236 end
237 device ref i2c3 on
238 chip drivers/i2c/tpm
239 register "hid" = ""GOOG0005""
240 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)"
241 device i2c 50 on end
242 end
243 end
244 device ref i2c5 on
245 chip drivers/i2c/generic
246 register "hid" = ""ELAN0000""
247 register "desc" = ""ELAN Touchpad""
248 register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)"
249 register "wake" = "GPE0_DW2_14"
250 register "probed" = "1"
251 device i2c 15 on end
252 end
253 chip drivers/i2c/hid
254 register "generic.hid" = ""GXTP7288""
255 register "generic.desc" = ""Goodix Touchpad""
256 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)"
257 register "generic.wake" = "GPE0_DW2_14"
258 register "generic.probed" = "1"
259 register "hid_desc_reg_offset" = "0x01"
260 device i2c 2c on end
261 end
262 end
263 device ref hda on
264 chip drivers/generic/max98357a
265 register "hid" = ""MX98360A""
266 register "sdmode_gpio" =
267 "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
268 register "sdmode_delay" = "5"
269 device generic 0 on
270 probe AUDIO MAX98360_ALC5682I_I2S
271 probe AUDIO MAX98360_ALC5682I_VS_I2S
272 end
273 end
274 end
275 device ref gspi1 on
276 chip drivers/spi/acpi
277 register "name" = ""CRFP""
278 register "hid" = "ACPI_DT_NAMESPACE_HID"
279 register "uid" = "1"
280 register "compat_string" = ""google,cros-ec-spi""
281 register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)"
282 register "wake" = "GPE0_DW2_15"
283 device spi 0 on end
284 end # FPMCU
285 end
286 device ref pch_espi on
287 chip ec/google/chromeec
288 use conn0 as mux_conn[0]
289 use conn1 as mux_conn[1]
290 device pnp 0c09.0 on end
291 end
292 end
293 device ref pmc hidden
294 chip drivers/intel/pmc_mux
295 device generic 0 on
296 chip drivers/intel/pmc_mux/conn
297 use usb2_port1 as usb2_port
298 use tcss_usb3_port1 as usb3_port
299 device generic 0 alias conn0 on end
300 end
301 chip drivers/intel/pmc_mux/conn
302 use usb2_port3 as usb2_port
303 use tcss_usb3_port3 as usb3_port
304 device generic 1 alias conn1 on end
305 end
306 end
307 end
308 end
309 device ref tcss_xhci on
310 chip drivers/usb/acpi
311 device ref tcss_root_hub on
312 chip drivers/usb/acpi
313 register "desc" = ""USB3 Type-C Port C0 (MLB)""
314 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
315 register "use_custom_pld" = "true"
316 register "custom_pld" = "{
317 .visible = true,
318 .panel = PLD_PANEL_LEFT,
319 .horizontal_position = PLD_HORIZONTAL_POSITION_CENTER,
320 .shape = PLD_SHAPE_OVAL,
321 .group = ACPI_PLD_GROUP(1, 1)}"
322 device ref tcss_usb3_port1 on end
323 end
324 chip drivers/usb/acpi
325 register "desc" = ""USB3 Type-C Port C2 (MLB)""
326 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
327 register "use_custom_pld" = "true"
328 register "custom_pld" = "{
329 .visible = true,
330 .panel = PLD_PANEL_LEFT,
331 .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT,
332 .shape = PLD_SHAPE_OVAL,
333 .group = ACPI_PLD_GROUP(2, 1)}"
334 device ref tcss_usb3_port3 on end
335 end
336 end
337 end
338 end
339 device ref xhci on
340 chip drivers/usb/acpi
341 device ref xhci_root_hub on
342 chip drivers/usb/acpi
343 register "desc" = ""USB2 Type-C Port C0 (MLB)""
344 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
345 register "use_custom_pld" = "true"
346 register "custom_pld" = "{
347 .visible = true,
348 .panel = PLD_PANEL_LEFT,
349 .horizontal_position = PLD_HORIZONTAL_POSITION_CENTER,
350 .shape = PLD_SHAPE_OVAL,
351 .group = ACPI_PLD_GROUP(1, 1)}"
352 device ref usb2_port1 on end
353 end
354 chip drivers/usb/acpi
355 register "desc" = ""USB2 Type-C Port C2 (MLB)""
356 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
357 register "use_custom_pld" = "true"
358 register "custom_pld" = "{
359 .visible = true,
360 .panel = PLD_PANEL_LEFT,
361 .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT,
362 .shape = PLD_SHAPE_OVAL,
363 .group = ACPI_PLD_GROUP(2, 1)}"
364 device ref usb2_port3 on end
365 end
366 chip drivers/usb/acpi
367 register "desc" = ""USB2 WWAN""
368 register "type" = "UPC_TYPE_INTERNAL"
369 device ref usb2_port4 on end
370 end
371 chip drivers/usb/acpi
372 register "desc" = ""USB2 Camera""
373 register "type" = "UPC_TYPE_INTERNAL"
374 device ref usb2_port6 on end
375 end
376 chip drivers/usb/acpi
377 register "desc" = ""USB2 Type-A Port (MLB)""
378 register "type" = "UPC_TYPE_A"
379 register "use_custom_pld" = "true"
380 register "custom_pld" = "{
381 .visible = true,
382 .panel = PLD_PANEL_LEFT,
383 .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT,
384 .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE,
385 .group = ACPI_PLD_GROUP(4, 1)}"
386 device ref usb2_port8 on end
387 end
388 chip drivers/usb/acpi
389 register "desc" = ""USB2 Type-A Port A0 (DB)""
390 register "type" = "UPC_TYPE_A"
391 register "use_custom_pld" = "true"
392 register "custom_pld" = "{
393 .visible = true,
394 .panel = PLD_PANEL_RIGHT,
395 .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT,
396 .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE,
397 .group = ACPI_PLD_GROUP(1, 2)}"
398 device ref usb2_port9 on end
399 end
400 chip drivers/usb/acpi
401 register "desc" = ""USB2 Bluetooth""
402 register "type" = "UPC_TYPE_INTERNAL"
403 register "reset_gpio" =
404 "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
405 device ref usb2_port10 on end
406 end
407 chip drivers/usb/acpi
408 register "desc" = ""USB3 Type-A Port A0 (DB)""
409 register "type" = "UPC_TYPE_USB3_A"
410 register "use_custom_pld" = "true"
411 register "custom_pld" = "{
412 .visible = true,
413 .panel = PLD_PANEL_RIGHT,
414 .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT,
415 .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE,
416 .group = ACPI_PLD_GROUP(1, 2)}"
417 device ref usb3_port1 on end
418 end
419 chip drivers/usb/acpi
420 register "desc" = ""USB3 Type-A Port (MLB)""
421 register "type" = "UPC_TYPE_USB3_A"
422 register "use_custom_pld" = "true"
423 register "custom_pld" = "{
424 .visible = true,
425 .panel = PLD_PANEL_LEFT,
426 .horizontal_position = PLD_HORIZONTAL_POSITION_LEFT,
427 .shape = PLD_SHAPE_HORIZONTAL_RECTANGLE,
428 .group = ACPI_PLD_GROUP(4, 1)}"
429 device ref usb3_port2 on end
430 end
431 chip drivers/usb/acpi
432 register "desc" = ""USB3 WWAN""
433 register "type" = "UPC_TYPE_INTERNAL"
434 device ref usb3_port4 on end
435 end
436 end
437 end
438 end
439 end
440 end
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