src/include/elog.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #ifndef ELOG_H_
  17 #define ELOG_H_
  18
  19 #include <compiler.h>
  20
  21 /* SMI command code for GSMI event logging */
  22 #define ELOG_GSMI_APM_CNT                 0xEF
  23
  24 #define MAX_EVENT_SIZE                    0x7F
  25
  26 /* End of log */
  27 #define ELOG_TYPE_EOL                     0xFF
  28
  29 /*
  30  * Standard SMBIOS event log types below 0x80
  31  */
  32 #define ELOG_TYPE_UNDEFINED_EVENT         0x00
  33 #define ELOG_TYPE_SINGLE_BIT_ECC_MEM_ERR  0x01
  34 #define ELOG_TYPE_MULTI_BIT_ECC_MEM_ERR   0x02
  35 #define ELOG_TYPE_MEM_PARITY_ERR          0x03
  36 #define ELOG_TYPE_BUS_TIMEOUT             0x04
  37 #define ELOG_TYPE_IO_CHECK                0x05
  38 #define ELOG_TYPE_SW_NMI                  0x06
  39 #define ELOG_TYPE_POST_MEM_RESIZE         0x07
  40 #define ELOG_TYPE_POST_ERR                0x08
  41 #define ELOG_TYPE_PCI_PERR                0x09
  42 #define ELOG_TYPE_PCI_SERR                0x0A
  43 #define ELOG_TYPE_CPU_FAIL                0x0B
  44 #define ELOG_TYPE_EISA_TIMEOUT            0x0C
  45 #define ELOG_TYPE_CORRECTABLE_MEMLOG_DIS  0x0D
  46 #define ELOG_TYPE_LOG_DISABLED            0x0E
  47 #define ELOG_TYPE_UNDEFINED_EVENT2        0x0F
  48 #define ELOG_TYPE_SYS_LIMIT_EXCEED        0x10
  49 #define ELOG_TYPE_ASYNC_HW_TIMER_EXPIRED  0x11
  50 #define ELOG_TYPE_SYS_CONFIG_INFO         0x12
  51 #define ELOG_TYPE_HDD_INFO                0x13
  52 #define ELOG_TYPE_SYS_RECONFIG            0x14
  53 #define ELOG_TYPE_CPU_ERROR               0x15
  54 #define ELOG_TYPE_LOG_CLEAR               0x16
  55 #define ELOG_TYPE_BOOT                    0x17
  56
  57 /*
  58  * Extended defined OEM event types start at 0x80
  59  */
  60
  61 /* OS/kernel events */
  62 #define ELOG_TYPE_OS_EVENT                0x81
  63
  64 /* Last event from coreboot */
  65 #define ELOG_TYPE_OS_BOOT                 0x90
  66
  67 /* Embedded controller event */
  68 #define ELOG_TYPE_EC_EVENT                0x91
  69 #define EC_EVENT_LID_CLOSED                  0x01
  70 #define EC_EVENT_LID_OPEN                    0x02
  71 #define EC_EVENT_POWER_BUTTON                0x03
  72 #define EC_EVENT_AC_CONNECTED                0x04
  73 #define EC_EVENT_AC_DISCONNECTED             0x05
  74 #define EC_EVENT_BATTERY_LOW                 0x06
  75 #define EC_EVENT_BATTERY_CRITICAL            0x07
  76 #define EC_EVENT_BATTERY                     0x08
  77 #define EC_EVENT_THERMAL_THRESHOLD           0x09
  78 #define EC_EVENT_DEVICE_EVENT                0x0a
  79 #define EC_EVENT_THERMAL                     0x0b
  80 #define EC_EVENT_USB_CHARGER                 0x0c
  81 #define EC_EVENT_KEY_PRESSED                 0x0d
  82 #define EC_EVENT_INTERFACE_READY             0x0e
  83 #define EC_EVENT_KEYBOARD_RECOVERY           0x0f
  84 #define EC_EVENT_THERMAL_SHUTDOWN            0x10
  85 #define EC_EVENT_BATTERY_SHUTDOWN            0x11
  86 #define EC_EVENT_FAN_ERROR                   0x12
  87 #define EC_EVENT_THROTTLE_STOP               0x13
  88 #define EC_EVENT_HANG_DETECT                 0x14
  89 #define EC_EVENT_HANG_REBOOT                 0x15
  90 #define EC_EVENT_PD_MCU                      0x16
  91 #define EC_EVENT_BATTERY_STATUS              0x17
  92 #define EC_EVENT_PANIC                       0x18
  93 #define EC_EVENT_KEYBOARD_FASTBOOT           0x19
  94 #define EC_EVENT_RTC                         0x1a
  95 #define EC_EVENT_MKBP                        0x1b
  96 #define EC_EVENT_USB_MUX                     0x1c
  97 #define EC_EVENT_MODE_CHANGE                 0x1d
  98 #define EC_EVENT_KEYBOARD_RECOVERY_HWREINIT  0x1e
  99 #define EC_EVENT_EXTENDED                    0x1f
 100
 101 /* Power */
 102 #define ELOG_TYPE_POWER_FAIL              0x92
 103 #define ELOG_TYPE_SUS_POWER_FAIL          0x93
 104 #define ELOG_TYPE_PWROK_FAIL              0x94
 105 #define ELOG_TYPE_SYS_PWROK_FAIL          0x95
 106 #define ELOG_TYPE_POWER_ON                0x96
 107 #define ELOG_TYPE_POWER_BUTTON            0x97
 108 #define ELOG_TYPE_POWER_BUTTON_OVERRIDE   0x98
 109
 110 /* Reset */
 111 #define ELOG_TYPE_RESET_BUTTON            0x99
 112 #define ELOG_TYPE_SYSTEM_RESET            0x9a
 113 #define ELOG_TYPE_RTC_RESET               0x9b
 114 #define ELOG_TYPE_TCO_RESET               0x9c
 115
 116 /* Sleep/Wake */
 117 #define ELOG_TYPE_ACPI_ENTER              0x9d
 118 /* Deep Sx wake variant is provided below - 0xad */
 119 #define ELOG_TYPE_ACPI_WAKE               0x9e
 120 #define ELOG_TYPE_WAKE_SOURCE             0x9f
 121 #define  ELOG_WAKE_SOURCE_PCIE             0x00
 122 #define  ELOG_WAKE_SOURCE_PME              0x01
 123 #define  ELOG_WAKE_SOURCE_PME_INTERNAL     0x02
 124 #define  ELOG_WAKE_SOURCE_RTC              0x03
 125 #define  ELOG_WAKE_SOURCE_GPIO             0x04
 126 #define  ELOG_WAKE_SOURCE_SMBUS            0x05
 127 #define  ELOG_WAKE_SOURCE_PWRBTN           0x06
 128 #define  ELOG_WAKE_SOURCE_PME_HDA          0x07
 129 #define  ELOG_WAKE_SOURCE_PME_GBE          0x08
 130 #define  ELOG_WAKE_SOURCE_PME_EMMC         0x09
 131 #define  ELOG_WAKE_SOURCE_PME_SDCARD       0x0a
 132 #define  ELOG_WAKE_SOURCE_PME_PCIE1        0x0b
 133 #define  ELOG_WAKE_SOURCE_PME_PCIE2        0x0c
 134 #define  ELOG_WAKE_SOURCE_PME_PCIE3        0x0d
 135 #define  ELOG_WAKE_SOURCE_PME_PCIE4        0x0e
 136 #define  ELOG_WAKE_SOURCE_PME_PCIE5        0x0f
 137 #define  ELOG_WAKE_SOURCE_PME_PCIE6        0x10
 138 #define  ELOG_WAKE_SOURCE_PME_PCIE7        0x11
 139 #define  ELOG_WAKE_SOURCE_PME_PCIE8        0x12
 140 #define  ELOG_WAKE_SOURCE_PME_PCIE9        0x13
 141 #define  ELOG_WAKE_SOURCE_PME_PCIE10       0x14
 142 #define  ELOG_WAKE_SOURCE_PME_PCIE11       0x15
 143 #define  ELOG_WAKE_SOURCE_PME_PCIE12       0x16
 144 #define  ELOG_WAKE_SOURCE_PME_SATA         0x17
 145 #define  ELOG_WAKE_SOURCE_PME_CSE          0x18
 146 #define  ELOG_WAKE_SOURCE_PME_CSE2         0x19
 147 #define  ELOG_WAKE_SOURCE_PME_CSE3         0x1a
 148 #define  ELOG_WAKE_SOURCE_PME_XHCI         0x1b
 149 #define  ELOG_WAKE_SOURCE_PME_XDCI         0x1c
 150 #define  ELOG_WAKE_SOURCE_PME_XHCI_USB_2   0x1d
 151 #define  ELOG_WAKE_SOURCE_PME_XHCI_USB_3   0x1e
 152 #define  ELOG_WAKE_SOURCE_PME_WIFI         0x1f
 153
 154 struct elog_event_data_wake {
 155         u8 source;
 156         u32 instance;
 157 } __packed;
 158
 159 /* Chrome OS related events */
 160 #define ELOG_TYPE_CROS_DEVELOPER_MODE     0xa0
 161 #define ELOG_TYPE_CROS_RECOVERY_MODE      0xa1
 162 #define  ELOG_CROS_RECOVERY_MODE_BUTTON    0x02
 163
 164 /* Management Engine Events */
 165 #define ELOG_TYPE_MANAGEMENT_ENGINE       0xa2
 166 #define ELOG_TYPE_MANAGEMENT_ENGINE_EXT   0xa4
 167 struct elog_event_data_me_extended {
 168         u8 current_working_state;
 169         u8 operation_state;
 170         u8 operation_mode;
 171         u8 error_code;
 172         u8 progress_code;
 173         u8 current_pmevent;
 174         u8 current_state;
 175 } __packed;
 176
 177 /* Last post code from previous boot */
 178 #define ELOG_TYPE_LAST_POST_CODE          0xa3
 179 #define ELOG_TYPE_POST_EXTRA              0xa6
 180
 181 /* EC Shutdown Reason */
 182 #define ELOG_TYPE_EC_SHUTDOWN             0xa5
 183
 184 /* ARM/generic versions of sleep/wake - These came from another firmware
 185  * apparently, but not all the firmware sources were updated so that the
 186  * elog namespace was coherent. */
 187 #define ELOG_TYPE_SLEEP                   0xa7
 188 #define ELOG_TYPE_WAKE                    0xa8
 189 #define ELOG_TYPE_FW_WAKE                 0xa9
 190
 191 /* Memory Cache Update */
 192 #define ELOG_TYPE_MEM_CACHE_UPDATE        0xaa
 193 #define  ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL    0
 194 #define  ELOG_MEM_CACHE_UPDATE_SLOT_RECOVERY  1
 195 #define  ELOG_MEM_CACHE_UPDATE_SLOT_VARIABLE  2
 196 #define  ELOG_MEM_CACHE_UPDATE_STATUS_SUCCESS 0
 197 #define  ELOG_MEM_CACHE_UPDATE_STATUS_FAIL    1
 198 struct elog_event_mem_cache_update {
 199         u8 slot;
 200         u8 status;
 201 } __packed;
 202
 203 /* CPU Thermal Trip */
 204 #define ELOG_TYPE_THERM_TRIP              0xab
 205
 206 /* Cr50 */
 207 #define ELOG_TYPE_CR50_UPDATE             0xac
 208
 209 /* Deep Sx wake variant */
 210 #define ELOG_TYPE_ACPI_DEEP_WAKE          0xad
 211
 212 /* EC Device Event */
 213 #define ELOG_TYPE_EC_DEVICE_EVENT         0xae
 214 #define ELOG_EC_DEVICE_EVENT_TRACKPAD       0x01
 215 #define ELOG_EC_DEVICE_EVENT_DSP            0x02
 216 #define ELOG_EC_DEVICE_EVENT_WIFI           0x03
 217
 218 /* S0ix sleep/wake */
 219 #define ELOG_TYPE_S0IX_ENTER              0xaf
 220 #define ELOG_TYPE_S0IX_EXIT               0xb0
 221
 222 #if IS_ENABLED(CONFIG_ELOG)
 223 /* Eventlog backing storage must be initialized before calling elog_init(). */
 224 extern int elog_init(void);
 225 extern int elog_clear(void);
 226 /* Event addition functions return < 0 on failure and 0 on success. */
 227 extern int elog_add_event_raw(u8 event_type, void *data, u8 data_size);
 228 extern int elog_add_event(u8 event_type);
 229 extern int elog_add_event_byte(u8 event_type, u8 data);
 230 extern int elog_add_event_word(u8 event_type, u16 data);
 231 extern int elog_add_event_dword(u8 event_type, u32 data);
 232 extern int elog_add_event_wake(u8 source, u32 instance);
 233 extern int elog_smbios_write_type15(unsigned long *current, int handle);
 234 #else
 235 /* Stubs to help avoid littering sources with #if CONFIG_ELOG */
 236 static inline int elog_init(void) { return -1; }
 237 static inline int elog_clear(void) { return -1; }
 238 static inline int elog_add_event_raw(u8 event_type, void *data,
 239                                         u8 data_size) { return 0; }
 240 static inline int elog_add_event(u8 event_type) { return 0; }
 241 static inline int elog_add_event_byte(u8 event_type, u8 data) { return 0; }
 242 static inline int elog_add_event_word(u8 event_type, u16 data) { return 0; }
 243 static inline int elog_add_event_dword(u8 event_type, u32 data) { return 0; }
 244 static inline int elog_add_event_wake(u8 source, u32 instance) { return 0; }
 245 static inline int elog_smbios_write_type15(unsigned long *current,
 246                                                 int handle) {
 247         return 0;
 248 }
 249 #endif
 250
 251 extern u32 gsmi_exec(u8 command, u32 *param);
 252
 253 #if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT)
 254 u32 boot_count_read(void);
 255 #else
 256 static inline u32 boot_count_read(void)
 257 {
 258         return 0;
 259 }
 260 #endif
 261 u32 boot_count_increment(void);
 262
 263 /*
 264  * Callback from GSMI handler to allow platform to log any wake source
 265  * information.
 266  */
 267 void elog_gsmi_cb_platform_log_wake_source(void);
 268
 269 /*
 270  * Callback from GSMI handler to allow mainboard to log any wake source
 271  * information.
 272  */
 273 void elog_gsmi_cb_mainboard_log_wake_source(void);
 274
 275 #endif /* ELOG_H_ */