src/southbridge/nvidia/mcp55/bootblock.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2004 Tyan Computer
   5  * Written by Yinghai Lu <yhlu@tyan.com> for Tyan Computer.
   6  * Copyright (C) 2006,2007 AMD
   7  * Written by Yinghai Lu <yinghai.lu@amd.com> for AMD.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  22  */
  23
  24 #include <stdint.h>
  25 #include <arch/io.h>
  26 #include "mcp55.h"
  27
  28 static void mcp55_enable_rom(void)
  29 {
  30         u8 byte;
  31         u16 word;
  32         pci_devfn_t addr;
  33
  34         /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */
  35 #if 0
  36         /* Default MCP55 LPC single */
  37         addr = pci_locate_device(PCI_ID(0x10de, 0x0367), 0);
  38 #else
  39 //      addr = pci_locate_device(PCI_ID(0x10de, 0x0360), 0);
  40         addr = PCI_DEV(0, (MCP55_DEVN_BASE + 1), 0);
  41 #endif
  42
  43         /* Set the 15MB enable bits. */
  44         byte = pci_read_config8(addr, 0x88);
  45         byte |= 0xff; /* 256K */
  46         pci_write_config8(addr, 0x88, byte);
  47         byte = pci_read_config8(addr, 0x8c);
  48         byte |= 0xff; /* 1M */
  49         pci_write_config8(addr, 0x8c, byte);
  50         word = pci_read_config16(addr, 0x90);
  51         word |= 0x7fff; /* 15M */
  52         pci_write_config16(addr, 0x90, word);
  53 }
  54
  55 static void bootblock_southbridge_init(void)
  56 {
  57         mcp55_enable_rom();
  58 }