mb/google/poppy/variants/nocturne: Add DMIC properties to ACPI DSD
[coreboot.git] / util / inteltool / ahci.c
blob6d539f437d8a2194b80a0b1e6e9bf5ae26d521ad
1 /*
2 * ahci.c: dump AHCI registers
4 * Copyright (C) 2016 Iru Cai
5 * Copyright (C) 2017 secunet Security Networks AG
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of the
10 * License.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
18 #include <stdio.h>
19 #include <stdlib.h>
20 #include <inttypes.h>
21 #include "inteltool.h"
23 static const char *ghc_regs[] = {
24 "CAP", "GHC", "IS", "PI",
25 "VS", "CCC_CTL", "CCC_PORTS", "EM_LOC",
26 "EM_CTL", "CAP2", "BOHC"
29 static const char *port_ctl_regs[] = {
30 "PxCLB", "PxCLBU", "PxFB", "PxFBU",
31 "PxIS", "PxIE", "PxCMD", "Reserved",
32 "PxTFD", "PxSIG", "PxSSTS", "PxSCTL",
33 "PxSERR", "PxSACT", "PxCI", "PxSNTF",
34 "PxFBS", "PxDEVSLP", "Reserved"
37 #define NUM_GHC (sizeof(ghc_regs)/sizeof(ghc_regs[0]))
38 #define NUM_PORTCTL (sizeof(port_ctl_regs)/sizeof(port_ctl_regs[0]))
40 #define MMIO(offset) (*(uint32_t *)(mmio + offset))
41 #define MMIO_PORT(offset) (*(uint32_t *)(mmio_port + offset))
43 static void print_port(const uint8_t *const mmio, size_t port)
45 size_t i;
46 printf("\nPort %zu Control Registers:\n", port);
47 const uint8_t *const mmio_port = mmio + 0x100 + port * 0x80;
48 for (i = 0; i < 0x80; i += 4) {
49 if (i / 4 < NUM_PORTCTL) {
50 printf("0x%03zx: 0x%08x (%s)\n",
51 (size_t)(mmio_port - mmio) + i,
52 MMIO_PORT(i), port_ctl_regs[i / 4]);
53 } else if (MMIO_PORT(i)) {
54 printf("0x%03zx: 0x%08x (Reserved)\n",
55 (size_t)(mmio_port - mmio) + i, MMIO_PORT(i));
60 int print_ahci(struct pci_dev *ahci)
62 size_t mmio_size, i;
64 if (!ahci) {
65 puts("No SATA device found");
66 return 0;
68 printf("\n============= AHCI Registers ==============\n\n");
70 if (ahci->device_id == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA)
71 mmio_size = 0x800;
72 else
73 mmio_size = 0x400;
75 const pciaddr_t mmio_phys = ahci->base_addr[5] & ~0x7ULL;
76 printf("ABAR = 0x%08llx (MEM)\n\n", (unsigned long long)mmio_phys);
77 const uint8_t *const mmio = map_physical(mmio_phys, mmio_size);
78 if (mmio == NULL) {
79 perror("Error mapping MMIO");
80 exit(1);
83 puts("Generic Host Control Registers:");
84 for (i = 0; i < 0x100; i += 4) {
85 if (i / 4 < NUM_GHC) {
86 printf("0x%03zx: 0x%08x (%s)\n",
87 i, MMIO(i), ghc_regs[i / 4]);
88 } else if (MMIO(i)) {
89 printf("0x%03zx: 0x%08x (Reserved)\n", i, MMIO(i));
93 const size_t max_ports = (mmio_size - 0x100) / 0x80;
94 for (i = 0; i < max_ports; i++) {
95 if (MMIO(0x0c) & 1 << i)
96 print_port(mmio, i);
99 if (ahci->device_id == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA) {
100 puts("\nOther registers:");
101 for (i = 0x500; i < mmio_size; i += 4) {
102 if (MMIO(i))
103 printf("0x%03zx: 0x%08x\n", i, MMIO(i));
107 unmap_physical((void *)mmio, mmio_size);
108 return 0;