src/device/pciexp_device.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2005 Linux Networx
   5  * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <console/console.h>
  18 #include <delay.h>
  19 #include <device/device.h>
  20 #include <device/pci.h>
  21 #include <device/pci_ids.h>
  22 #include <device/pciexp.h>
  23
  24 unsigned int pciexp_find_extended_cap(device_t dev, unsigned int cap)
  25 {
  26         unsigned int this_cap_offset, next_cap_offset;
  27         unsigned int this_cap, cafe;
  28
  29         this_cap_offset = PCIE_EXT_CAP_OFFSET;
  30         do {
  31                 this_cap = pci_read_config32(dev, this_cap_offset);
  32                 next_cap_offset = this_cap >> 20;
  33                 this_cap &= 0xffff;
  34                 cafe = pci_read_config32(dev, this_cap_offset + 4);
  35                 cafe &= 0xffff;
  36                 if (this_cap == cap)
  37                         return this_cap_offset;
  38                 else if (cafe == cap)
  39                         return this_cap_offset + 4;
  40                 else
  41                         this_cap_offset = next_cap_offset;
  42         } while (next_cap_offset != 0);
  43
  44         return 0;
  45 }
  46
  47 /*
  48  * Re-train a PCIe link
  49  */
  50 #define PCIE_TRAIN_RETRY 10000
  51 static int pciexp_retrain_link(device_t dev, unsigned cap)
  52 {
  53         unsigned try = PCIE_TRAIN_RETRY;
  54         u16 lnk;
  55
  56         /* Start link retraining */
  57         lnk = pci_read_config16(dev, cap + PCI_EXP_LNKCTL);
  58         lnk |= PCI_EXP_LNKCTL_RL;
  59         pci_write_config16(dev, cap + PCI_EXP_LNKCTL, lnk);
  60
  61         /* Wait for training to complete */
  62         while (try--) {
  63                 lnk = pci_read_config16(dev, cap + PCI_EXP_LNKSTA);
  64                 if (!(lnk & PCI_EXP_LNKSTA_LT))
  65                         return 0;
  66                 udelay(100);
  67         }
  68
  69         printk(BIOS_ERR, "%s: Link Retrain timeout\n", dev_path(dev));
  70         return -1;
  71 }
  72
  73 /*
  74  * Check the Slot Clock Configuration for root port and endpoint
  75  * and enable Common Clock Configuration if possible.  If CCC is
  76  * enabled the link must be retrained.
  77  */
  78 static void pciexp_enable_common_clock(device_t root, unsigned root_cap,
  79                                        device_t endp, unsigned endp_cap)
  80 {
  81         u16 root_scc, endp_scc, lnkctl;
  82
  83         /* Get Slot Clock Configuration for root port */
  84         root_scc = pci_read_config16(root, root_cap + PCI_EXP_LNKSTA);
  85         root_scc &= PCI_EXP_LNKSTA_SLC;
  86
  87         /* Get Slot Clock Configuration for endpoint */
  88         endp_scc = pci_read_config16(endp, endp_cap + PCI_EXP_LNKSTA);
  89         endp_scc &= PCI_EXP_LNKSTA_SLC;
  90
  91         /* Enable Common Clock Configuration and retrain */
  92         if (root_scc && endp_scc) {
  93                 printk(BIOS_INFO, "Enabling Common Clock Configuration\n");
  94
  95                 /* Set in endpoint */
  96                 lnkctl = pci_read_config16(endp, endp_cap + PCI_EXP_LNKCTL);
  97                 lnkctl |= PCI_EXP_LNKCTL_CCC;
  98                 pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl);
  99
 100                 /* Set in root port */
 101                 lnkctl = pci_read_config16(root, root_cap + PCI_EXP_LNKCTL);
 102                 lnkctl |= PCI_EXP_LNKCTL_CCC;
 103                 pci_write_config16(root, root_cap + PCI_EXP_LNKCTL, lnkctl);
 104
 105                 /* Retrain link if CCC was enabled */
 106                 pciexp_retrain_link(root, root_cap);
 107         }
 108 }
 109
 110 static void pciexp_enable_clock_power_pm(device_t endp, unsigned endp_cap)
 111 {
 112         /* check if per port clk req is supported in device */
 113         u32 endp_ca;
 114         u16 lnkctl;
 115         endp_ca = pci_read_config32(endp, endp_cap + PCI_EXP_LNKCAP);
 116         if ((endp_ca & PCI_EXP_CLK_PM) == 0) {
 117                 printk(BIOS_INFO, "PCIE CLK PM is not supported by endpoint");
 118                 return;
 119         }
 120         lnkctl = pci_read_config16(endp, endp_cap + PCI_EXP_LNKCTL);
 121         lnkctl = lnkctl | PCI_EXP_EN_CLK_PM;
 122         pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl);
 123 }
 124
 125 static void pciexp_config_max_latency(device_t root, device_t dev)
 126 {
 127         unsigned int cap;
 128         cap = pciexp_find_extended_cap(dev, PCIE_EXT_CAP_LTR_ID);
 129         if ((cap) && (root->ops->ops_pci != NULL) &&
 130                 (root->ops->ops_pci->set_L1_ss_latency != NULL))
 131                         root->ops->ops_pci->set_L1_ss_latency(dev, cap + 4);
 132 }
 133
 134 static void pciexp_enable_ltr(device_t dev)
 135 {
 136         unsigned int cap;
 137         cap = pci_find_capability(dev, PCI_CAP_ID_PCIE);
 138         if(!cap) {
 139                 printk(BIOS_INFO, "Failed to enable LTR for dev = %s\n",
 140                         dev_path(dev));
 141                 return;
 142         }
 143         pci_update_config32(dev, cap + 0x28, ~(1 << 10), 1 << 10);
 144 }
 145
 146 static unsigned char pciexp_L1_substate_cal(device_t dev, unsigned int endp_cap,
 147         unsigned int *data)
 148 {
 149         unsigned char mult[4] = {2, 10, 100, 0};
 150
 151         unsigned int L1SubStateSupport = *data & 0xf;
 152         unsigned int comm_mode_rst_time = (*data >> 8) & 0xff;
 153         unsigned int power_on_scale = (*data >> 16) & 0x3;
 154         unsigned int power_on_value = (*data >> 19) & 0x1f;
 155
 156         unsigned int endp_data = pci_read_config32(dev, endp_cap + 4);
 157         unsigned int endp_L1SubStateSupport = endp_data & 0xf;
 158         unsigned int endp_comm_mode_restore_time = (endp_data >> 8) & 0xff;
 159         unsigned int endp_power_on_scale = (endp_data >> 16) & 0x3;
 160         unsigned int endp_power_on_value = (endp_data >> 19) & 0x1f;
 161
 162         L1SubStateSupport &= endp_L1SubStateSupport;
 163
 164         if (L1SubStateSupport == 0)
 165                 return 0;
 166
 167         if (power_on_value * mult[power_on_scale] <
 168                 endp_power_on_value * mult[endp_power_on_scale]) {
 169                 power_on_value = endp_power_on_value;
 170                 power_on_scale = endp_power_on_scale;
 171         }
 172         if (comm_mode_rst_time < endp_comm_mode_restore_time)
 173                 comm_mode_rst_time = endp_comm_mode_restore_time;
 174
 175         *data = (comm_mode_rst_time << 8) | (power_on_scale << 16)
 176                 | (power_on_value << 19) | L1SubStateSupport;
 177
 178         return 1;
 179 }
 180
 181 static void pciexp_L1_substate_commit(device_t root, device_t dev,
 182         unsigned int root_cap, unsigned int end_cap)
 183 {
 184         device_t dev_t;
 185         unsigned char L1_ss_ok;
 186         unsigned int rp_L1_support = pci_read_config32(root, root_cap + 4);
 187         unsigned int L1SubStateSupport;
 188         unsigned int comm_mode_rst_time;
 189         unsigned int power_on_scale;
 190         unsigned int endp_power_on_value;
 191
 192         for (dev_t = dev; dev_t; dev_t = dev_t->sibling) {
 193                 /*
 194                  * rp_L1_support is init'd above from root port.
 195                  * it needs coordination with endpoints to reach in common.
 196                  * if certain endpoint doesn't support L1 Sub-State, abort
 197                  * this feature enabling.
 198                  */
 199                 L1_ss_ok = pciexp_L1_substate_cal(dev_t, end_cap,
 200                                                 &rp_L1_support);
 201                 if (!L1_ss_ok)
 202                         return;
 203         }
 204
 205         L1SubStateSupport = rp_L1_support & 0xf;
 206         comm_mode_rst_time = (rp_L1_support >> 8) & 0xff;
 207         power_on_scale = (rp_L1_support >> 16) & 0x3;
 208         endp_power_on_value = (rp_L1_support >> 19) & 0x1f;
 209
 210         printk(BIOS_INFO, "L1 Sub-State supported from root port %d\n",
 211                 root->path.pci.devfn >> 3);
 212         printk(BIOS_INFO, "L1 Sub-State Support = 0x%x\n", L1SubStateSupport);
 213         printk(BIOS_INFO, "CommonModeRestoreTime = 0x%x\n", comm_mode_rst_time);
 214         printk(BIOS_INFO, "Power On Value = 0x%x, Power On Scale = 0x%x\n",
 215                 endp_power_on_value, power_on_scale);
 216
 217         pciexp_enable_ltr(root);
 218
 219         pci_update_config32(root, root_cap + 0x08, ~0xff00,
 220                 (comm_mode_rst_time << 8));
 221
 222         pci_update_config32(root, root_cap + 0x0c , 0xffffff04,
 223                 (endp_power_on_value << 3) | (power_on_scale));
 224
 225         pci_update_config32(root, root_cap + 0x08, ~0xe3ff0000,
 226                 (1 << 21) | (1 << 23) | (1 << 30));
 227
 228         pci_update_config32(root, root_cap + 0x08, ~0x1f,
 229                 L1SubStateSupport);
 230
 231         for (dev_t = dev; dev_t; dev_t = dev_t->sibling) {
 232                 pci_update_config32(dev_t, end_cap + 0x0c , 0xffffff04,
 233                         (endp_power_on_value << 3) | (power_on_scale));
 234
 235                 pci_update_config32(dev_t, end_cap + 0x08, ~0xe3ff0000,
 236                         (1 << 21) | (1 << 23) | (1 << 30));
 237
 238                 pci_update_config32(dev_t, end_cap + 0x08, ~0x1f,
 239                         L1SubStateSupport);
 240
 241                 pciexp_enable_ltr(dev_t);
 242
 243                 pciexp_config_max_latency(root, dev_t);
 244         }
 245 }
 246
 247 static void pciexp_config_L1_sub_state(device_t root, device_t dev)
 248 {
 249         unsigned int root_cap, end_cap;
 250
 251         /* Do it for function 0 only */
 252         if (dev->path.pci.devfn & 0x7)
 253                 return;
 254
 255         root_cap = pciexp_find_extended_cap(root, PCIE_EXT_CAP_L1SS_ID);
 256         if (!root_cap)
 257                 return;
 258
 259         end_cap = pciexp_find_extended_cap(dev, PCIE_EXT_CAP_L1SS_ID);
 260         if (!end_cap) {
 261                 end_cap = pciexp_find_extended_cap(dev, 0xcafe);
 262                 if (!end_cap)
 263                         return;
 264         }
 265
 266         pciexp_L1_substate_commit(root, dev, root_cap, end_cap);
 267 }
 268
 269 /*
 270  * Determine the ASPM L0s or L1 exit latency for a link
 271  * by checking both root port and endpoint and returning
 272  * the highest latency value.
 273  */
 274 static int pciexp_aspm_latency(device_t root, unsigned root_cap,
 275                                device_t endp, unsigned endp_cap,
 276                                enum aspm_type type)
 277 {
 278         int root_lat = 0, endp_lat = 0;
 279         u32 root_lnkcap, endp_lnkcap;
 280
 281         root_lnkcap = pci_read_config32(root, root_cap + PCI_EXP_LNKCAP);
 282         endp_lnkcap = pci_read_config32(endp, endp_cap + PCI_EXP_LNKCAP);
 283
 284         /* Make sure the link supports this ASPM type by checking
 285          * capability bits 11:10 with aspm_type offset by 1 */
 286         if (!(root_lnkcap & (1 << (type + 9))) ||
 287             !(endp_lnkcap & (1 << (type + 9))))
 288                 return -1;
 289
 290         /* Find the one with higher latency */
 291         switch (type) {
 292         case PCIE_ASPM_L0S:
 293                 root_lat = (root_lnkcap & PCI_EXP_LNKCAP_L0SEL) >> 12;
 294                 endp_lat = (endp_lnkcap & PCI_EXP_LNKCAP_L0SEL) >> 12;
 295                 break;
 296         case PCIE_ASPM_L1:
 297                 root_lat = (root_lnkcap & PCI_EXP_LNKCAP_L1EL) >> 15;
 298                 endp_lat = (endp_lnkcap & PCI_EXP_LNKCAP_L1EL) >> 15;
 299                 break;
 300         default:
 301                 return -1;
 302         }
 303
 304         return (endp_lat > root_lat) ? endp_lat : root_lat;
 305 }
 306
 307 /*
 308  * Enable ASPM on PCIe root port and endpoint.
 309  */
 310 static void pciexp_enable_aspm(device_t root, unsigned root_cap,
 311                                          device_t endp, unsigned endp_cap)
 312 {
 313         const char *aspm_type_str[] = { "None", "L0s", "L1", "L0s and L1" };
 314         enum aspm_type apmc = PCIE_ASPM_NONE;
 315         int exit_latency, ok_latency;
 316         u16 lnkctl;
 317         u32 devcap;
 318
 319         /* Get endpoint device capabilities for acceptable limits */
 320         devcap = pci_read_config32(endp, endp_cap + PCI_EXP_DEVCAP);
 321
 322         /* Enable L0s if it is within endpoint acceptable limit */
 323         ok_latency = (devcap & PCI_EXP_DEVCAP_L0S) >> 6;
 324         exit_latency = pciexp_aspm_latency(root, root_cap, endp, endp_cap,
 325                                            PCIE_ASPM_L0S);
 326         if (exit_latency >= 0 && exit_latency <= ok_latency)
 327                 apmc |= PCIE_ASPM_L0S;
 328
 329         /* Enable L1 if it is within endpoint acceptable limit */
 330         ok_latency = (devcap & PCI_EXP_DEVCAP_L1) >> 9;
 331         exit_latency = pciexp_aspm_latency(root, root_cap, endp, endp_cap,
 332                                            PCIE_ASPM_L1);
 333         if (exit_latency >= 0 && exit_latency <= ok_latency)
 334                 apmc |= PCIE_ASPM_L1;
 335
 336         if (apmc != PCIE_ASPM_NONE) {
 337                 /* Set APMC in root port first */
 338                 lnkctl = pci_read_config16(root, root_cap + PCI_EXP_LNKCTL);
 339                 lnkctl |= apmc;
 340                 pci_write_config16(root, root_cap + PCI_EXP_LNKCTL, lnkctl);
 341
 342                 /* Set APMC in endpoint device next */
 343                 lnkctl = pci_read_config16(endp, endp_cap + PCI_EXP_LNKCTL);
 344                 lnkctl |= apmc;
 345                 pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl);
 346
 347                 /* Enable ASPM role based error reporting. */
 348                 devcap = pci_read_config32(endp, endp_cap + PCI_EXP_DEVCAP);
 349                 devcap |= PCI_EXP_DEVCAP_RBER;
 350                 pci_write_config32(endp, endp_cap + PCI_EXP_DEVCAP, devcap);
 351         }
 352
 353         printk(BIOS_INFO, "ASPM: Enabled %s\n", aspm_type_str[apmc]);
 354 }
 355
 356 static void pciexp_tune_dev(device_t dev)
 357 {
 358         device_t root = dev->bus->dev;
 359         unsigned int root_cap, cap;
 360
 361         cap = pci_find_capability(dev, PCI_CAP_ID_PCIE);
 362         if (!cap)
 363                 return;
 364
 365         root_cap = pci_find_capability(root, PCI_CAP_ID_PCIE);
 366         if (!root_cap)
 367                 return;
 368
 369         /* Check for and enable Common Clock */
 370         if (IS_ENABLED(CONFIG_PCIEXP_COMMON_CLOCK))
 371                 pciexp_enable_common_clock(root, root_cap, dev, cap);
 372
 373         /* Check if per port CLK req is supported by endpoint*/
 374         if (IS_ENABLED(CONFIG_PCIEXP_CLK_PM))
 375                 pciexp_enable_clock_power_pm(dev, cap);
 376
 377         /* Enable L1 Sub-State when both root port and endpoint support */
 378         if (IS_ENABLED(CONFIG_PCIEXP_L1_SUB_STATE))
 379                 pciexp_config_L1_sub_state(root, dev);
 380
 381         /* Check for and enable ASPM */
 382         if (IS_ENABLED(CONFIG_PCIEXP_ASPM))
 383                 pciexp_enable_aspm(root, root_cap, dev, cap);
 384 }
 385
 386 void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn,
 387                              unsigned int max_devfn)
 388 {
 389         device_t child;
 390
 391         pci_scan_bus(bus, min_devfn, max_devfn);
 392
 393         for (child = bus->children; child; child = child->sibling) {
 394                 if ((child->path.pci.devfn < min_devfn) ||
 395                     (child->path.pci.devfn > max_devfn)) {
 396                         continue;
 397                 }
 398                 pciexp_tune_dev(child);
 399         }
 400 }
 401
 402 void pciexp_scan_bridge(device_t dev)
 403 {
 404         do_pci_scan_bridge(dev, pciexp_scan_bus);
 405 }
 406
 407 /** Default device operations for PCI Express bridges */
 408 static struct pci_operations pciexp_bus_ops_pci = {
 409         .set_subsystem = 0,
 410 };
 411
 412 struct device_operations default_pciexp_ops_bus = {
 413         .read_resources   = pci_bus_read_resources,
 414         .set_resources    = pci_dev_set_resources,
 415         .enable_resources = pci_bus_enable_resources,
 416         .init             = 0,
 417         .scan_bus         = pciexp_scan_bridge,
 418         .enable           = 0,
 419         .reset_bus        = pci_bus_reset,
 420         .ops_pci          = &pciexp_bus_ops_pci,
 421 };