src/mainboard/ocp/deltalake/romstage.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <console/console.h>
   4 #include <drivers/ipmi/ipmi_kcs.h>
   5 #include <drivers/vpd/vpd.h>
   6 #include <fsp/api.h>
   7 #include <FspmUpd.h>
   8 #include <soc/romstage.h>
   9 #include <string.h>
  10
  11 #include "chip.h"
  12 #include "ipmi.h"
  13 #include "vpd.h"
  14
  15 /*
  16  * Search from VPD_RW first then VPD_RO for UPD config variables,
  17  * overwrites them from VPD if it's found.
  18  */
  19 static void mainboard_config_upd(FSPM_UPD *mupd)
  20 {
  21         uint8_t val;
  22         int val_int;
  23
  24         /* Send FSP log message to SOL */
  25         if (vpd_get_bool(FSP_LOG, VPD_RW_THEN_RO, &val))
  26                 mupd->FspmConfig.SerialIoUartDebugEnable = val;
  27         else {
  28                 printk(BIOS_INFO, "Not able to get VPD %s, default set "
  29                         "SerialIoUartDebugEnable to %d\n", FSP_LOG, FSP_LOG_DEFAULT);
  30                 mupd->FspmConfig.SerialIoUartDebugEnable = FSP_LOG_DEFAULT;
  31         }
  32         mupd->FspmConfig.SerialIoUartDebugIoBase = 0x2f8;
  33
  34         if (mupd->FspmConfig.SerialIoUartDebugEnable) {
  35                 /* FSP debug log level */
  36                 if (vpd_get_int(FSP_LOG_LEVEL, VPD_RW_THEN_RO, &val_int)) {
  37                         if (val_int < 0 || val_int > 0x0f) {
  38                                 printk(BIOS_DEBUG, "Invalid DebugPrintLevel value from VPD: "
  39                                         "%d\n", val_int);
  40                                 val_int = FSP_LOG_LEVEL_DEFAULT;
  41                         }
  42                         printk(BIOS_DEBUG, "Setting DebugPrintLevel %d from VPD\n", val_int);
  43                         mupd->FspmConfig.DebugPrintLevel = (uint8_t)val_int;
  44                 } else {
  45                         printk(BIOS_INFO, "Not able to get VPD %s, default set "
  46                                 "DebugPrintLevel to %d\n", FSP_LOG_LEVEL,
  47                                 FSP_LOG_LEVEL_DEFAULT);
  48                         mupd->FspmConfig.DebugPrintLevel = FSP_LOG_LEVEL_DEFAULT;
  49                 }
  50         }
  51
  52         /* Enable DCI */
  53         if (vpd_get_bool(FSP_DCI, VPD_RW_THEN_RO, &val)) {
  54                 printk(BIOS_DEBUG, "Setting DciEn %d from VPD\n", val);
  55                 mupd->FspmConfig.PchDciEn = val;
  56         } else {
  57                 printk(BIOS_INFO, "Not able to get VPD %s, default set "
  58                         "DciEn to %d\n", FSP_DCI, FSP_DCI_DEFAULT);
  59                 mupd->FspmConfig.PchDciEn = FSP_DCI_DEFAULT;
  60         }
  61
  62         /*
  63          * UnusedUpdSpace0[0] is reserved for Memory Refresh Watermark.
  64          * Following code is effective when MemRefreshWaterMark patch is added to FSP
  65          * and when corresponding VPD variable is set.
  66          */
  67         if (vpd_get_int(FSPM_MEMREFRESHWATERMARK, VPD_RW_THEN_RO, &val_int)) {
  68                 if (val_int < 0 || val_int > 2) {
  69                         printk(BIOS_DEBUG, "Invalid MemRefreshWatermark value from VPD: "
  70                                 "%d\n", val_int);
  71                         val_int = FSPM_MEMREFRESHWATERMARK_DEFAULT;
  72                 }
  73                 printk(BIOS_DEBUG, "Setting MemRefreshWatermark %d from VPD\n", val_int);
  74                 mupd->FspmConfig.UnusedUpdSpace0[0] = (uint8_t)val_int;
  75         }
  76 }
  77
  78 /* Update bifurcation settings according to different Configs */
  79 static void oem_update_iio(FSPM_UPD *mupd)
  80 {
  81         uint8_t pcie_config = 0;
  82
  83         /* Default set to PCIE_CONFIG_C first */
  84         mupd->FspmConfig.IioConfigIOU0[0] = IIO_BIFURCATE_x4x4x4x4;
  85         mupd->FspmConfig.IioConfigIOU1[0] = IIO_BIFURCATE_x4x4x4x4;
  86         mupd->FspmConfig.IioConfigIOU2[0] = IIO_BIFURCATE_xxxxxxxx;
  87         mupd->FspmConfig.IioConfigIOU3[0] = IIO_BIFURCATE_xxxxxx16;
  88         mupd->FspmConfig.IioConfigIOU4[0] = IIO_BIFURCATE_xxxxxxxx;
  89         /* Update IIO bifurcation according to different Configs */
  90         if (ipmi_get_pcie_config(&pcie_config) == CB_SUCCESS) {
  91                 printk(BIOS_DEBUG, "get IPMI PCIe config: %d\n", pcie_config);
  92                 switch (pcie_config) {
  93                 case PCIE_CONFIG_A:
  94                         mupd->FspmConfig.IioConfigIOU0[0] = IIO_BIFURCATE_xxxxxxxx;
  95                         mupd->FspmConfig.IioConfigIOU3[0] = IIO_BIFURCATE_xxxxxxxx;
  96                         break;
  97                 case PCIE_CONFIG_B:
  98                         mupd->FspmConfig.IioConfigIOU0[0] = IIO_BIFURCATE_xxxxxxxx;
  99                         mupd->FspmConfig.IioConfigIOU3[0] = IIO_BIFURCATE_x4x4x4x4;
 100                         break;
 101                 case PCIE_CONFIG_D:
 102                         mupd->FspmConfig.IioConfigIOU3[0] = IIO_BIFURCATE_x4x4x4x4;
 103                         break;
 104                 case PCIE_CONFIG_C:
 105                 default:
 106                         break;
 107                 }
 108         } else {
 109                 printk(BIOS_ERR, "%s failed to get IPMI PCIe config\n", __func__);
 110         }
 111 }
 112
 113 /*
 114 * Configure GPIO depend on platform
 115 */
 116 static void mainboard_config_gpios(FSPM_UPD *mupd)
 117 {
 118         /* To be implemented */
 119 }
 120
 121 static void mainboard_config_iio(FSPM_UPD *mupd)
 122 {
 123         uint8_t index;
 124         const config_t *config = config_of_soc();
 125
 126         oem_update_iio(mupd);
 127
 128         for (index = 0; index < MAX_PCH_PCIE_PORT; index++) {
 129                 mupd->FspmConfig.PchPcieForceEnable[index] =
 130                         config->pch_pci_port[index].ForceEnable;
 131                 mupd->FspmConfig.PchPciePortLinkSpeed[index] =
 132                         config->pch_pci_port[index].PortLinkSpeed;
 133         }
 134
 135         mupd->FspmConfig.PchPcieRootPortFunctionSwap = 0x00;
 136         /* The default value is 0XFF in FSP, set it to 0xFE by platform */
 137         mupd->FspmConfig.PchPciePllSsc = 0xFE;
 138 }
 139
 140 void mainboard_memory_init_params(FSPM_UPD *mupd)
 141 {
 142         /* Since it's the first IPMI command, it's better to run get BMC
 143            selftest result first */
 144         if (ipmi_kcs_premem_init(CONFIG_BMC_KCS_BASE, 0) == CB_SUCCESS) {
 145                 ipmi_set_post_start(CONFIG_BMC_KCS_BASE);
 146                 init_frb2_wdt();
 147         }
 148
 149         mainboard_config_gpios(mupd);
 150         mainboard_config_iio(mupd);
 151         mainboard_config_upd(mupd);
 152 }
 153
 154 void mainboard_rtc_failed(void)
 155 {
 156         if (ipmi_set_cmos_clear() == CB_SUCCESS)
 157                 printk(BIOS_DEBUG, "%s: IPMI set cmos clear successful\n", __func__);
 158         else
 159                 printk(BIOS_ERR, "%s: IPMI set cmos clear failed\n", __func__);
 160 }