2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
5 ## Copyright (C) 2009-2010 coresystems GmbH
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; version 2 of the License.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
17 mainmenu "coreboot configuration"
22 string "Local version string"
24 Append an extra string to the end of the coreboot version.
26 This can be useful if, for instance, you want to append the
27 respective board's hostname or some other identifying string to
28 the coreboot version number, so that you can easily distinguish
29 boot logs of different boards from each other.
32 string "CBFS prefix to use"
35 Select the prefix to all files put into the image. It's "fallback"
36 by default, "normal" is a common alternative.
38 config COMMON_CBFS_SPI_WRAPPER
44 Use common wrapper to interface CBFS to SPI bootrom.
46 config MULTIPLE_CBFS_INSTANCES
47 bool "Multiple CBFS instances in the bootrom"
50 Account for the firmware image containing more than one CBFS
51 instance. Locations of instances are known at build time and are
52 communicated between coreboot stages to make sure the next stage is
53 loaded from the appropriate instance.
56 prompt "Compiler to use"
59 This option allows you to select the compiler used for building
61 You must build the coreboot crosscompiler for the board that you
64 To build all the GCC crosscompilers (takes a LONG time), run:
67 For help on individual architectures, run the command:
73 Use the GNU Compiler Collection (GCC) to build coreboot.
75 For details see http://gcc.gnu.org.
77 config COMPILER_LLVM_CLANG
78 bool "LLVM/clang (TESTING ONLY - Not currently working)"
80 Use LLVM/clang to build coreboot. To use this, you must build the
81 coreboot version of the clang compiler. Run the command
83 Note that this option is not currently working correctly and should
84 really only be selected if you're trying to work on getting clang
87 For details see http://clang.llvm.org.
92 bool "Allow building with any toolchain"
94 depends on COMPILER_GCC
96 Many toolchains break when building coreboot since it uses quite
97 unusual linker features. Unless developers explicitely request it,
98 we'll have to assume that they use their distro compiler by mistake.
99 Make sure that using patched compilers is a conscious decision.
102 bool "Use ccache to speed up (re)compilation"
105 Enables the use of ccache for faster builds.
107 Requires the ccache utility in your system $PATH.
109 For details see https://ccache.samba.org.
112 bool "Generate flashmap descriptor parser using flex and bison"
115 Enable this option if you are working on the flashmap descriptor
116 parser and made changes to fmd_scanner.l or fmd_parser.y.
118 Otherwise, say N to use the provided pregenerated scanner/parser.
120 config SCONFIG_GENPARSER
121 bool "Generate SCONFIG parser using flex and bison"
124 Enable this option if you are working on the sconfig device tree
125 parser and made changes to sconfig.l or sconfig.y.
127 Otherwise, say N to use the provided pregenerated scanner/parser.
129 config USE_OPTION_TABLE
130 bool "Use CMOS for configuration values"
132 depends on HAVE_OPTION_TABLE
134 Enable this option if coreboot shall read options from the "CMOS"
135 NVRAM instead of using hard-coded values.
137 config STATIC_OPTION_TABLE
138 bool "Load default configuration values into CMOS on each boot"
140 depends on USE_OPTION_TABLE
142 Enable this option to reset "CMOS" NVRAM values to default on
143 every boot. Use this if you want the NVRAM configuration to
144 never be modified from its default values.
146 config UNCOMPRESSED_RAMSTAGE
150 config COMPRESS_RAMSTAGE
151 bool "Compress ramstage with LZMA"
152 default y if !UNCOMPRESSED_RAMSTAGE
155 Compress ramstage to save memory in the flash image. Note
156 that decompression might slow down booting if the boot flash
157 is connected through a slow link (i.e. SPI).
159 config COMPRESS_PRERAM_STAGES
160 bool "Compress romstage and verstage with LZ4"
164 Compress romstage and (if it exists) verstage with LZ4 to save flash
165 space and speed up boot, since the time for reading the image from SPI
166 (and in the vboot case verifying it) is usually much greater than the
167 time spent decompressing. Doesn't work for XIP stages (assume all
168 ARCH_X86 for now) for obvious reasons.
170 config INCLUDE_CONFIG_FILE
171 bool "Include the coreboot .config file into the ROM image"
174 Include the .config file that was used to compile coreboot
175 in the (CBFS) ROM image. This is useful if you want to know which
176 options were used to build a specific coreboot.rom image.
178 Saying Y here will increase the image size by 2-3KB.
180 You can use the following command to easily list the options:
182 grep -a CONFIG_ coreboot.rom
184 Alternatively, you can also use cbfstool to print the image
185 contents (including the raw 'config' item we're looking for).
189 $ cbfstool coreboot.rom print
190 coreboot.rom: 4096 kB, bootblocksize 1008, romsize 4194304,
194 Name Offset Type Size
195 cmos_layout.bin 0x0 cmos layout 1159
196 fallback/romstage 0x4c0 stage 339756
197 fallback/ramstage 0x53440 stage 186664
198 fallback/payload 0x80dc0 payload 51526
199 config 0x8d740 raw 3324
200 (empty) 0x8e480 null 3610440
202 config EARLY_CBMEM_INIT
203 def_bool !LATE_CBMEM_INIT
205 config COLLECT_TIMESTAMPS
206 bool "Create a table of timestamps collected during boot"
209 Make coreboot create a table of timer-ID/timer-value pairs to
210 allow measuring time spent at different phases of the boot process.
213 bool "Allow use of binary-only repository"
216 This draws in the blobs repository, which contains binary files that
217 might be required for some chipsets or boards.
218 This flag ensures that a "Free" option remains available for users.
221 bool "Code coverage support"
222 depends on COMPILER_GCC
225 Add code coverage support for coreboot. This will store code
226 coverage information in CBMEM for extraction from user space.
229 config RELOCATABLE_MODULES
233 If RELOCATABLE_MODULES is selected then support is enabled for
234 building relocatable modules in the RAM stage. Those modules can be
235 loaded anywhere and all the relocations are handled automatically.
237 config RELOCATABLE_RAMSTAGE
238 depends on EARLY_CBMEM_INIT
239 bool "Build the ramstage to be relocatable in 32-bit address space."
241 select RELOCATABLE_MODULES
243 The reloctable ramstage support allows for the ramstage to be built
244 as a relocatable module. The stage loader can identify a place
245 out of the OS way so that copying memory is unnecessary during an S3
246 wake. When selecting this option the romstage is responsible for
247 determing a stack location to use for loading the ramstage.
249 config CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
250 depends on RELOCATABLE_RAMSTAGE
251 bool "Cache the relocated ramstage outside of cbmem."
254 The relocated ramstage is saved in an area specified by the
255 by the board and/or chipset.
257 config FLASHMAP_OFFSET
258 hex "Flash Map Offset"
259 default 0x00670000 if NORTHBRIDGE_INTEL_SANDYBRIDGE
260 default 0x00610000 if NORTHBRIDGE_INTEL_IVYBRIDGE
261 default CBFS_SIZE if !ARCH_X86
264 Offset of flash map in firmware image
266 # TODO: This doesn't belong here, move to src/arch/x86/Kconfig
268 prompt "Bootblock behaviour"
269 default BOOTBLOCK_SIMPLE
271 config BOOTBLOCK_SIMPLE
272 bool "Always load fallback"
274 config BOOTBLOCK_NORMAL
275 bool "Switch to normal if CMOS says so"
279 # To be selected by arch, SoC or mainboard if it does not want use the normal
280 # src/lib/bootblock.c#main() C entry point.
281 config BOOTBLOCK_CUSTOM
285 config BOOTBLOCK_SOURCE
287 default "bootblock_simple.c" if BOOTBLOCK_SIMPLE
288 default "bootblock_normal.c" if BOOTBLOCK_NORMAL
290 # To be selected by arch or platform if a C environment is available during the
291 # bootblock. Normally this signifies availability of RW memory (e.g. SRAM).
292 config C_ENVIRONMENT_BOOTBLOCK
296 config SKIP_MAX_REBOOT_CNT_CLEAR
297 bool "Do not clear reboot count after successful boot"
299 depends on BOOTBLOCK_NORMAL
301 Do not clear the reboot count immediately after successful boot.
302 Set to allow the payload to control normal/fallback image recovery.
303 Note that it is the responsibility of the payload to reset the
304 normal boot bit to 1 after each successsful boot.
307 bool "Update existing coreboot.rom image"
310 If this option is enabled, no new coreboot.rom file
311 is created. Instead it is expected that there already
312 is a suitable file for further processing.
313 The bootblock will not be modified.
315 If unsure, select 'N'
317 config GENERIC_GPIO_LIB
321 If enabled, compile the generic GPIO library. A "generic" GPIO
322 implies configurability usually found on SoCs, particularly the
323 ability to control internal pull resistors.
329 Mainboards that can read a board ID from the hardware straps
330 (ie. GPIO) select this configuration option.
332 config BOARD_ID_MANUAL
335 depends on !BOARD_ID_AUTO
337 If you want to maintain a board ID, but the hardware does not
338 have straps to automatically determine the ID, you can say Y
339 here and add a file named 'board_id' to CBFS. If you don't know
340 what this is about, say N.
342 config BOARD_ID_STRING
345 depends on BOARD_ID_MANUAL
347 This string is placed in the 'board_id' CBFS file for indicating
350 config RAM_CODE_SUPPORT
354 If enabled, coreboot discovers RAM configuration (value obtained by
355 reading board straps) and stores it in coreboot table.
357 config BOOTSPLASH_IMAGE
358 bool "Add a bootsplash image"
360 Select this option if you have a bootsplash image that you would
361 like to add to your ROM.
363 This will only add the image to the ROM. To actually run it check
364 options under 'Display' section.
366 config BOOTSPLASH_FILE
367 string "Bootsplash path and filename"
368 depends on BOOTSPLASH_IMAGE
369 default "bootsplash.jpg"
371 The path and filename of the file to use as graphical bootsplash
372 screen. The file format has to be jpg.
376 source "src/acpi/Kconfig"
380 source "src/mainboard/Kconfig"
382 # defaults for CBFS_SIZE are set at the end of the file.
384 hex "Size of CBFS filesystem in ROM"
386 This is the part of the ROM actually managed by CBFS, located at the
387 end of the ROM (passed through cbfstool -o) on x86 and at at the start
388 of the ROM (passed through cbfstool -s) everywhere else. It defaults
389 to span the whole ROM on all but Intel systems that use an Intel Firmware
390 Descriptor. It can be overridden to make coreboot live alongside other
391 components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE
395 string "fmap description file in fmd format"
396 default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS
399 The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
400 but in some cases more complex setups are required.
401 When an fmd is specified, it overrides the default format.
405 # load site-local kconfig to allow user specific defaults and overrides
406 source "site-local/Kconfig"
408 config SYSTEM_TYPE_LAPTOP
412 config CBFS_AUTOGEN_ATTRIBUTES
416 If this option is selected, every file in cbfs which has a constraint
417 regarding position or alignment will get an additional file attribute
418 which describes this constraint.
423 source "src/soc/*/*/Kconfig"
425 source "src/cpu/Kconfig"
426 comment "Northbridge"
427 source "src/northbridge/*/*/Kconfig"
428 comment "Southbridge"
429 source "src/southbridge/*/*/Kconfig"
431 source "src/superio/*/Kconfig"
432 comment "Embedded Controllers"
433 source "src/ec/acpi/Kconfig"
434 source "src/ec/*/*/Kconfig"
435 source "src/drivers/intel/fsp1_0/Kconfig"
437 source "src/southbridge/intel/common/firmware/Kconfig"
438 source "src/vendorcode/*/Kconfig"
440 source "src/arch/*/Kconfig"
444 source "src/device/Kconfig"
446 menu "Generic Drivers"
447 source "src/drivers/*/Kconfig"
457 select LPC_TPM if ARCH_X86
458 select I2C_TPM if ARCH_ARM
459 select I2C_TPM if ARCH_ARM64
461 Enable this option to enable TPM support in coreboot.
476 default 0x1000 if ARCH_X86
483 config MMCONF_SUPPORT_DEFAULT
487 config MMCONF_SUPPORT
491 config BOOTMODE_STRAPS
495 source "src/console/Kconfig"
497 config HAVE_ACPI_RESUME
501 config RESUME_PATH_SAME_AS_BOOT
503 default y if ARCH_X86
504 depends on HAVE_ACPI_RESUME
506 This option indicates that when a system resumes it takes the
507 same path as a regular boot. e.g. an x86 system runs from the
508 reset vector at 0xfffffff0 on both resume and warm/cold boot.
510 config HAVE_HARD_RESET
514 This variable specifies whether a given board has a hard_reset
515 function, no matter if it's provided by board code or chipset code.
517 config HAVE_ROMSTAGE_CONSOLE_SPINLOCK
521 config HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK
525 This should be enabled on certain plaforms, such as the AMD
526 SR565x, that cannot handle concurrent CBFS accesses from
527 multiple APs during early startup.
529 config HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK
533 config HAVE_MONOTONIC_TIMER
536 The board/chipset provides a monotonic timer.
538 config GENERIC_UDELAY
540 depends on HAVE_MONOTONIC_TIMER
542 The board/chipset uses a generic udelay function utilizing the
547 depends on HAVE_MONOTONIC_TIMER
549 Provide a timer queue for performing time-based callbacks.
551 config COOP_MULTITASKING
553 depends on TIMER_QUEUE && ARCH_X86
555 Cooperative multitasking allows callbacks to be multiplexed on the
556 main thread of ramstage. With this enabled it allows for multiple
557 execution paths to take place when they have udelay() calls within
563 depends on COOP_MULTITASKING
565 How many execution threads to cooperatively multitask with.
567 config HAVE_OPTION_TABLE
571 This variable specifies whether a given board has a cmos.layout
572 file containing NVRAM/CMOS bit definitions.
573 It defaults to 'n' but can be selected in mainboard/*/Kconfig.
579 config HAVE_SMI_HANDLER
583 config PCI_IO_CFG_EXT
591 config CACHE_ROM_SIZE_OVERRIDE
595 # TODO: Can probably be removed once all chipsets have kconfig options for it.
600 config USE_WATCHDOG_ON_BOOT
608 Build board-specific VGA code.
614 Enable Unified Memory Architecture for graphics.
616 config HAVE_ACPI_TABLES
619 This variable specifies whether a given board has ACPI table support.
620 It is usually set in mainboard/*/Kconfig.
625 This variable specifies whether a given board has MP table support.
626 It is usually set in mainboard/*/Kconfig.
627 Whether or not the MP table is actually generated by coreboot
628 is configurable by the user via GENERATE_MP_TABLE.
630 config HAVE_PIRQ_TABLE
633 This variable specifies whether a given board has PIRQ table support.
634 It is usually set in mainboard/*/Kconfig.
635 Whether or not the PIRQ table is actually generated by coreboot
636 is configurable by the user via GENERATE_PIRQ_TABLE.
638 config MAX_PIRQ_LINKS
642 This variable specifies the number of PIRQ interrupt links which are
643 routable. On most chipsets, this is 4, INTA through INTD. Some
644 chipsets offer more than four links, commonly up to INTH. They may
645 also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
646 table specifies links greater than 4, pirq_route_irqs will not
647 function properly, unless this variable is correctly set.
657 Build support for NHLT (non HD Audio) ACPI table generation.
659 #These Options are here to avoid "undefined" warnings.
660 #The actual selection and help texts are in the following menu.
664 config GENERATE_MP_TABLE
665 prompt "Generate an MP table" if HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
667 default HAVE_MP_TABLE || DRIVERS_GENERIC_IOAPIC
669 Generate an MP table (conforming to the Intel MultiProcessor
670 specification 1.4) for this board.
674 config GENERATE_PIRQ_TABLE
675 prompt "Generate a PIRQ table" if HAVE_PIRQ_TABLE
677 default HAVE_PIRQ_TABLE
679 Generate a PIRQ table for this board.
683 config GENERATE_SMBIOS_TABLES
685 bool "Generate SMBIOS tables"
688 Generate SMBIOS tables for this board.
692 config SMBIOS_PROVIDED_BY_MOBO
696 config MAINBOARD_SERIAL_NUMBER
697 string "SMBIOS Serial Number"
698 depends on GENERATE_SMBIOS_TABLES
699 depends on !SMBIOS_PROVIDED_BY_MOBO
702 The Serial Number to store in SMBIOS structures.
704 config MAINBOARD_VERSION
705 string "SMBIOS Version Number"
706 depends on GENERATE_SMBIOS_TABLES
707 depends on !SMBIOS_PROVIDED_BY_MOBO
710 The Version Number to store in SMBIOS structures.
712 config MAINBOARD_SMBIOS_MANUFACTURER
713 string "SMBIOS Manufacturer"
714 depends on GENERATE_SMBIOS_TABLES
715 depends on !SMBIOS_PROVIDED_BY_MOBO
716 default MAINBOARD_VENDOR
718 Override the default Manufacturer stored in SMBIOS structures.
720 config MAINBOARD_SMBIOS_PRODUCT_NAME
721 string "SMBIOS Product name"
722 depends on GENERATE_SMBIOS_TABLES
723 depends on !SMBIOS_PROVIDED_BY_MOBO
724 default MAINBOARD_PART_NUMBER
726 Override the default Product name stored in SMBIOS structures.
730 source "payloads/Kconfig"
734 # TODO: Better help text and detailed instructions.
736 bool "GDB debugging support"
738 depends on CONSOLE_SERIAL
740 If enabled, you will be able to set breakpoints for gdb debugging.
741 See src/arch/x86/lib/c_start.S for details.
744 bool "Wait for a GDB connection"
748 If enabled, coreboot will wait for a GDB connection.
751 bool "Halt when hitting a BUG() or assertion error"
754 If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().
757 bool "Output verbose CBFS debug messages"
760 This option enables additional CBFS related debug messages.
762 config HAVE_DEBUG_RAM_SETUP
765 config DEBUG_RAM_SETUP
766 bool "Output verbose RAM init debug messages"
768 depends on HAVE_DEBUG_RAM_SETUP
770 This option enables additional RAM init related debug messages.
771 It is recommended to enable this when debugging issues on your
772 board which might be RAM init related.
774 Note: This option will increase the size of the coreboot image.
778 config HAVE_DEBUG_CAR
783 depends on HAVE_DEBUG_CAR
785 if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
786 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
787 # printk(BIOS_DEBUG, ...) calls.
789 bool "Output verbose Cache-as-RAM debug messages"
791 depends on HAVE_DEBUG_CAR
793 This option enables additional CAR related debug messages.
797 bool "Check PIRQ table consistency"
799 depends on GENERATE_PIRQ_TABLE
803 config HAVE_DEBUG_SMBUS
807 bool "Output verbose SMBus debug messages"
809 depends on HAVE_DEBUG_SMBUS
811 This option enables additional SMBus (and SPD) debug messages.
813 Note: This option will increase the size of the coreboot image.
818 bool "Output verbose SMI debug messages"
820 depends on HAVE_SMI_HANDLER
821 select SPI_FLASH_SMM if SPI_CONSOLE
823 This option enables additional SMI related debug messages.
825 Note: This option will increase the size of the coreboot image.
829 config DEBUG_SMM_RELOCATION
830 bool "Debug SMM relocation code"
832 depends on HAVE_SMI_HANDLER
834 This option enables additional SMM handler relocation related
837 Note: This option will increase the size of the coreboot image.
841 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
842 # printk(BIOS_DEBUG, ...) calls.
844 prompt "Output verbose malloc debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
848 This option enables additional malloc related debug messages.
850 Note: This option will increase the size of the coreboot image.
854 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
855 # printk(BIOS_DEBUG, ...) calls.
857 prompt "Output verbose ACPI debug messages" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
861 This option enables additional ACPI related debug messages.
863 Note: This option will slightly increase the size of the coreboot image.
867 # Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
868 # printk(BIOS_DEBUG, ...) calls.
869 config REALMODE_DEBUG
870 prompt "Enable debug messages for option ROM execution" if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
873 depends on PCI_OPTION_ROM_RUN_REALMODE
875 This option enables additional x86emu related debug messages.
877 Note: This option will increase the time to emulate a ROM.
882 bool "Output verbose x86emu debug messages"
884 depends on PCI_OPTION_ROM_RUN_YABEL
886 This option enables additional x86emu related debug messages.
888 Note: This option will increase the size of the coreboot image.
892 config X86EMU_DEBUG_JMP
893 bool "Trace JMP/RETF"
895 depends on X86EMU_DEBUG
897 Print information about JMP and RETF opcodes from x86emu.
899 Note: This option will increase the size of the coreboot image.
903 config X86EMU_DEBUG_TRACE
904 bool "Trace all opcodes"
906 depends on X86EMU_DEBUG
908 Print _all_ opcodes that are executed by x86emu.
910 WARNING: This will produce a LOT of output and take a long time.
912 Note: This option will increase the size of the coreboot image.
916 config X86EMU_DEBUG_PNP
917 bool "Log Plug&Play accesses"
919 depends on X86EMU_DEBUG
921 Print Plug And Play accesses made by option ROMs.
923 Note: This option will increase the size of the coreboot image.
927 config X86EMU_DEBUG_DISK
930 depends on X86EMU_DEBUG
932 Print Disk I/O related messages.
934 Note: This option will increase the size of the coreboot image.
938 config X86EMU_DEBUG_PMM
941 depends on X86EMU_DEBUG
943 Print messages related to POST Memory Manager (PMM).
945 Note: This option will increase the size of the coreboot image.
950 config X86EMU_DEBUG_VBE
951 bool "Debug VESA BIOS Extensions"
953 depends on X86EMU_DEBUG
955 Print messages related to VESA BIOS Extension (VBE) functions.
957 Note: This option will increase the size of the coreboot image.
961 config X86EMU_DEBUG_INT10
962 bool "Redirect INT10 output to console"
964 depends on X86EMU_DEBUG
966 Let INT10 (i.e. character output) calls print messages to debug output.
968 Note: This option will increase the size of the coreboot image.
972 config X86EMU_DEBUG_INTERRUPTS
973 bool "Log intXX calls"
975 depends on X86EMU_DEBUG
977 Print messages related to interrupt handling.
979 Note: This option will increase the size of the coreboot image.
983 config X86EMU_DEBUG_CHECK_VMEM_ACCESS
984 bool "Log special memory accesses"
986 depends on X86EMU_DEBUG
988 Print messages related to accesses to certain areas of the virtual
989 memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
991 Note: This option will increase the size of the coreboot image.
995 config X86EMU_DEBUG_MEM
996 bool "Log all memory accesses"
998 depends on X86EMU_DEBUG
1000 Print memory accesses made by option ROM.
1001 Note: This also includes accesses to fetch instructions.
1003 Note: This option will increase the size of the coreboot image.
1007 config X86EMU_DEBUG_IO
1008 bool "Log IO accesses"
1010 depends on X86EMU_DEBUG
1012 Print I/O accesses made by option ROM.
1014 Note: This option will increase the size of the coreboot image.
1018 config X86EMU_DEBUG_TIMINGS
1019 bool "Output timing information"
1021 depends on X86EMU_DEBUG && UDELAY_LAPIC && HAVE_MONOTONIC_TIMER
1023 Print timing information needed by i915tool.
1028 bool "Output verbose TPM debug messages"
1032 This option enables additional TPM related debug messages.
1034 config DEBUG_SPI_FLASH
1035 bool "Output verbose SPI flash debug messages"
1037 depends on SPI_FLASH
1039 This option enables additional SPI flash related debug messages.
1041 config DEBUG_USBDEBUG
1042 bool "Output verbose USB 2.0 EHCI debug dongle messages"
1046 This option enables additional USB 2.0 debug dongle related messages.
1048 Select this to debug the connection of usbdebug dongle. Note that
1049 you need some other working console to receive the messages.
1051 if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8
1052 # Only visible with the right southbridge and loglevel.
1053 config DEBUG_INTEL_ME
1054 bool "Verbose logging for Intel Management Engine"
1057 Enable verbose logging for Intel Management Engine driver that
1058 is present on Intel 6-series chipsets.
1062 bool "Trace function calls"
1065 If enabled, every function will print information to console once
1066 the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
1067 the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
1068 of calling function. Please note some printk related functions
1069 are omitted from trace to have good looking console dumps.
1071 config DEBUG_COVERAGE
1072 bool "Debug code coverage"
1076 If enabled, the code coverage hooks in coreboot will output some
1077 information about the coverage data that is dumped.
1081 # These probably belong somewhere else, but they are needed somewhere.
1082 config ENABLE_APIC_EXT_ID
1086 config WARNINGS_ARE_ERRORS
1090 # TODO: Remove this when all platforms are fixed.
1091 config IASL_WARNINGS_ARE_ERRORS
1094 Select to Fail the build if a IASL generates a warning.
1095 This will be defaulted to disabled for the platforms that
1096 currently fail. This allows the REST of the platforms to
1097 have this check enabled while we're working to get those
1100 DO NOT ADD TO ANY ADDITIONAL PLATFORMS INSTEAD OF FIXING
1103 # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
1104 # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
1105 # mutually exclusive. One of these options must be selected in the
1106 # mainboard Kconfig if the chipset supports enabling and disabling of
1107 # the power button. Chipset code uses the ENABLE_POWER_BUTTON option set
1108 # in mainboard/Kconfig to know if the button should be enabled or not.
1110 config POWER_BUTTON_DEFAULT_ENABLE
1113 Select when the board has a power button which can optionally be
1114 disabled by the user.
1116 config POWER_BUTTON_DEFAULT_DISABLE
1119 Select when the board has a power button which can optionally be
1120 enabled by the user, e.g. when the board ships with a jumper over
1121 the power switch contacts.
1123 config POWER_BUTTON_FORCE_ENABLE
1126 Select when the board requires that the power button is always
1129 config POWER_BUTTON_FORCE_DISABLE
1132 Select when the board requires that the power button is always
1133 disabled, e.g. when it has been hardwired to ground.
1135 config POWER_BUTTON_IS_OPTIONAL
1137 default y if POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE
1138 default n if !(POWER_BUTTON_DEFAULT_ENABLE || POWER_BUTTON_DEFAULT_DISABLE)
1140 Internal option that controls ENABLE_POWER_BUTTON visibility.
1146 Internal option that controls whether we compile in register scripts.
1148 config MAX_REBOOT_CNT
1152 Internal option that sets the maximum number of bootblock executions allowed
1153 with the normal image enabled before assuming the normal image is defective
1154 and switching to the fallback image.
1160 This is the part of the ROM actually managed by CBFS. Set it to be
1161 equal to the full rom size if that hasn't been overridden by the
1162 chipset or mainboard.
1164 config DEBUG_BOOT_STATE
1168 Control debugging of the boot state machine. When selected displays
1169 the state boundaries in ramstage.