src/mainboard/google/kahlee/mainboard.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <string.h>
   4 #include <console/console.h>
   5 #include <device/device.h>
   6 #include <device/mmio.h>
   7 #include <acpi/acpi.h>
   8 #include <amdblocks/agesawrapper.h>
   9 #include <amdblocks/amd_pci_util.h>
  10 #include <amdblocks/smi.h>
  11 #include <baseboard/variants.h>
  12 #include <boardid.h>
  13 #include <smbios.h>
  14 #include <soc/pci_devs.h>
  15 #include <soc/southbridge.h>
  16 #include <soc/smi.h>
  17 #include <amdblocks/acpimmio.h>
  18 #include <variant/ec.h>
  19 #include <variant/thermal.h>
  20 #include <vendorcode/google/chromeos/chromeos.h>
  21
  22 /***********************************************************
  23  * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
  24  * This table is responsible for physically routing the PIC and
  25  * IOAPIC IRQs to the different PCI devices on the system.  It
  26  * is read and written via registers 0xC00/0xC01 as an
  27  * Index/Data pair.  These values are chipset and mainboard
  28  * dependent and should be updated accordingly.
  29  *
  30  * These values are used by the PCI configuration space,
  31  * MP Tables.  TODO: Make ACPI use these values too.
  32  */
  33
  34 static const u8 mainboard_picr_data[] = {
  35         [0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x1F, 0x1F, 0x1F,
  36         [0x08] = 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
  37         [0x10] = 0x09, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x03,
  38         [0x18] = 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  39         [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00,
  40         [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  41         [0x30] = 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05,
  42         [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  43         [0x40] = 0x04, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  44         [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  45         [0x50] = 0x03, 0x04, 0x05, 0x07, 0x1F, 0x1F, 0x1F, 0x1F,
  46         [0x58] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
  47         [0x60] = 0x1F, 0x1F, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
  48         [0x68] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
  49         [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F,
  50         [0x78] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F,
  51 };
  52
  53 static const u8 mainboard_intr_data[] = {
  54         [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x1F, 0x16, 0x17,
  55         [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F,
  56         [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F, 0x10,
  57         [0x18] = 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00,
  58         [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00,
  59         [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  60         [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00,
  61         [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  62         [0x40] = 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  63         [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  64         [0x50] = 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00,
  65         [0x58] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  66         [0x60] = 0x1F, 0x1F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00,
  67         [0x68] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  68         [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F,
  69         [0x78] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  70 };
  71
  72 /*
  73  * This table defines the index into the picr/intr_data tables for each
  74  * device.  Any enabled device and slot that uses hardware interrupts should
  75  * have an entry in this table to define its index into the FCH PCI_INTR
  76  * register 0xC00/0xC01.  This index will define the interrupt that it should
  77  *  use. Putting PIRQ_A into the PIN A index for a device will tell that
  78  * device to use PIC IRQ 10 if it uses PIN A for its hardware INT.
  79  */
  80 static const struct pirq_struct mainboard_pirq_data[] = {
  81         { PCIE0_DEVFN,  { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } },
  82         { PCIE1_DEVFN,  { PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A } },
  83         { PCIE2_DEVFN,  { PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B } },
  84         { PCIE3_DEVFN,  { PIRQ_D, PIRQ_A, PIRQ_B, PIRQ_C } },
  85         { PCIE4_DEVFN,  { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } },
  86         { HDA0_DEVFN,   { PIRQ_NC, PIRQ_HDA, PIRQ_NC, PIRQ_NC } },
  87         { SD_DEVFN,     { PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC } },
  88         { SMBUS_DEVFN,  { PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC } },
  89         { SATA_DEVFN,   { PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC } },
  90         { EHCI1_DEVFN,  { PIRQ_EHCI, PIRQ_NC, PIRQ_NC, PIRQ_NC } },
  91         { XHCI_DEVFN,   { PIRQ_XHCI, PIRQ_NC, PIRQ_NC, PIRQ_NC } },
  92 };
  93
  94 /* PIRQ Setup */
  95 static void pirq_setup(void)
  96 {
  97         pirq_data_ptr = mainboard_pirq_data;
  98         pirq_data_size = ARRAY_SIZE(mainboard_pirq_data);
  99         intr_data_ptr = mainboard_intr_data;
 100         picr_data_ptr = mainboard_picr_data;
 101 }
 102
 103 static void mainboard_init(void *chip_info)
 104 {
 105         const struct sci_source *gpes;
 106         size_t num;
 107         int boardid = board_id();
 108         size_t num_gpios;
 109         const struct soc_amd_gpio *gpios;
 110
 111         printk(BIOS_INFO, "Board ID: %d\n", boardid);
 112
 113         mainboard_ec_init();
 114
 115         gpios = variant_gpio_table(&num_gpios);
 116         program_gpios(gpios, num_gpios);
 117
 118         /*
 119          * Some platforms use SCI not generated by a GPIO pin (event above 23).
 120          * For these boards, gpe_configure_sci() is still needed, but all GPIO
 121          * generated events (23-0) must be removed from gpe_table[].
 122          * For boards that only have GPIO generated events, table gpe_table[]
 123          * must be removed, and get_gpe_table() should return NULL.
 124          */
 125         gpes = get_gpe_table(&num);
 126         if (gpes != NULL)
 127                 gpe_configure_sci(gpes, num);
 128
 129         /* Initialize i2c busses that were not initialized in bootblock */
 130         i2c_soc_init();
 131
 132         /* Set GenIntDisable so that GPIO 90 is configured as a GPIO. */
 133         pm_write8(PM_PCIB_CFG, pm_read8(PM_PCIB_CFG) | PM_GENINT_DISABLE);
 134
 135         /* Set low-power mode for BayHub eMMC bridge's PCIe clock. */
 136         clrsetbits32(acpimmio_misc + GPP_CLK_CNTRL,
 137                      GPP_CLK2_REQ_MAP_MASK,
 138                      GPP_CLK2_REQ_MAP_CLK_REQ2 <<
 139                      GPP_CLK2_REQ_MAP_SHIFT);
 140
 141         /* Same for the WiFi */
 142         clrsetbits32(acpimmio_misc + GPP_CLK_CNTRL,
 143                      GPP_CLK0_REQ_MAP_MASK,
 144                      GPP_CLK0_REQ_MAP_CLK_REQ0 <<
 145                      GPP_CLK0_REQ_MAP_SHIFT);
 146 }
 147
 148 /*************************************************
 149  * Dedicated mainboard function
 150  *************************************************/
 151 static void mainboard_enable(struct device *dev)
 152 {
 153         /* Initialize the PIRQ data structures for consumption */
 154         pirq_setup();
 155
 156         dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
 157 }
 158
 159 int mainboard_get_xhci_oc_map(uint16_t *map)
 160 {
 161         return variant_get_xhci_oc_map(map);
 162 }
 163
 164 int mainboard_get_ehci_oc_map(uint16_t *map)
 165 {
 166         return variant_get_ehci_oc_map(map);
 167 }
 168
 169 void mainboard_suspend_resume(void)
 170 {
 171         variant_mainboard_suspend_resume();
 172 }
 173
 174 struct chip_operations mainboard_ops = {
 175         .init = mainboard_init,
 176         .enable_dev = mainboard_enable,
 177 };
 178
 179 /* Variants may override these functions so see definitions in variants/ */
 180 uint8_t __weak variant_board_sku(void)
 181 {
 182         return 0;
 183 }
 184
 185 void __weak variant_mainboard_suspend_resume(void)
 186 {
 187 }
 188
 189 const char *smbios_system_sku(void)
 190 {
 191         static char sku_str[7]; /* sku{0..255} */
 192
 193         snprintf(sku_str, sizeof(sku_str), "sku%d", variant_board_sku());
 194
 195         return sku_str;
 196 }