src/mainboard/amd/majolica/mainboard.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <amdblocks/amd_pci_util.h>
   4 #include <commonlib/helpers.h>
   5 #include <console/console.h>
   6 #include <device/device.h>
   7 #include <soc/acpi.h>
   8 #include <string.h>
   9 #include <types.h>
  10
  11 /*
  12  * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
  13  * This table is responsible for physically routing the PIC and
  14  * IOAPIC IRQs to the different PCI devices on the system.  It
  15  * is read and written via registers 0xC00/0xC01 as an
  16  * Index/Data pair.  These values are chipset and mainboard
  17  * dependent and should be updated accordingly.
  18  */
  19 static uint8_t fch_pic_routing[0x80];
  20 static uint8_t fch_apic_routing[0x80];
  21
  22 _Static_assert(sizeof(fch_pic_routing) == sizeof(fch_apic_routing),
  23         "PIC and APIC FCH interrupt tables must be the same size");
  24
  25 /*
  26  * This controls the device -> IRQ routing.
  27  *
  28  * Hardcoded IRQs:
  29  *  0: timer < soc/amd/common/acpi/lpc.asl
  30  *  1: i8042 - Keyboard
  31  *  2: cascade
  32  *  8: rtc0 <- soc/amd/common/acpi/lpc.asl
  33  *  9: acpi <- soc/amd/common/acpi/lpc.asl
  34  */
  35 static const struct fch_irq_routing {
  36         uint8_t intr_index;
  37         uint8_t pic_irq_num;
  38         uint8_t apic_irq_num;
  39 } majolica_fch[] = {
  40         { PIRQ_A,       PIRQ_NC,        PIRQ_NC },
  41         { PIRQ_B,       PIRQ_NC,        PIRQ_NC },
  42         { PIRQ_C,       PIRQ_NC,        PIRQ_NC },
  43         { PIRQ_D,       PIRQ_NC,        PIRQ_NC },
  44         { PIRQ_E,       PIRQ_NC,        PIRQ_NC },
  45         { PIRQ_F,       PIRQ_NC,        PIRQ_NC },
  46         { PIRQ_G,       PIRQ_NC,        PIRQ_NC },
  47         { PIRQ_H,       PIRQ_NC,        PIRQ_NC },
  48
  49         { PIRQ_SCI,     ACPI_SCI_IRQ,   ACPI_SCI_IRQ },
  50         { PIRQ_SD,      PIRQ_NC,        PIRQ_NC },
  51         { PIRQ_SDIO,    PIRQ_NC,        PIRQ_NC },
  52         { PIRQ_SATA,    PIRQ_NC,        PIRQ_NC },
  53         { PIRQ_EMMC,    PIRQ_NC,        PIRQ_NC },
  54         { PIRQ_GPIO,    PIRQ_NC,        PIRQ_NC },
  55         { PIRQ_I2C2,    PIRQ_NC,        PIRQ_NC },
  56         { PIRQ_I2C3,    PIRQ_NC,        PIRQ_NC },
  57         { PIRQ_UART0,    4,              4 },
  58         { PIRQ_UART1,    3,              3 },
  59
  60         /* The MISC registers are not interrupt numbers */
  61         { PIRQ_MISC,    0xfa,           0x00 },
  62         { PIRQ_MISC0,   0x91,           0x00 },
  63         { PIRQ_HPET_L,  0x00,           0x00 },
  64         { PIRQ_HPET_H,  0x00,           0x00 },
  65 };
  66
  67 static void init_tables(void)
  68 {
  69         const struct fch_irq_routing *entry;
  70         int i;
  71
  72         memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing));
  73         memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing));
  74
  75         for (i = 0; i < ARRAY_SIZE(majolica_fch); i++) {
  76                 entry = majolica_fch + i;
  77                 fch_pic_routing[entry->intr_index] = entry->pic_irq_num;
  78                 fch_apic_routing[entry->intr_index] = entry->apic_irq_num;
  79         }
  80 }
  81
  82 static void pirq_setup(void)
  83 {
  84         intr_data_ptr = fch_apic_routing;
  85         picr_data_ptr = fch_pic_routing;
  86 }
  87
  88 static void mainboard_init(void *chip_info)
  89 {
  90 }
  91
  92 static void mainboard_enable(struct device *dev)
  93 {
  94         init_tables();
  95         /* Initialize the PIRQ data structures for consumption */
  96         pirq_setup();
  97 }
  98
  99 struct chip_operations mainboard_ops = {
 100         .init = mainboard_init,
 101         .enable_dev = mainboard_enable,
 102 };