src/soc/amd/stoneyridge/chip.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2017 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <chip.h>
  17 #include <bootstate.h>
  18 #include <console/console.h>
  19 #include <cpu/amd/mtrr.h>
  20 #include <cpu/cpu.h>
  21 #include <device/device.h>
  22 #include <device/pci.h>
  23 #include <soc/cpu.h>
  24 #include <soc/northbridge.h>
  25 #include <soc/pci_devs.h>
  26 #include <soc/southbridge.h>
  27 #include <amdblocks/psp.h>
  28 #include <amdblocks/agesawrapper.h>
  29 #include <amdblocks/agesawrapper_call.h>
  30
  31 struct device_operations cpu_bus_ops = {
  32         .read_resources   = DEVICE_NOOP,
  33         .set_resources    = DEVICE_NOOP,
  34         .enable_resources = DEVICE_NOOP,
  35         .init             = stoney_init_cpus,
  36         .acpi_fill_ssdt_generator = generate_cpu_entries,
  37 };
  38
  39 static const char *soc_acpi_name(const struct device *dev)
  40 {
  41         if (dev->path.type == DEVICE_PATH_DOMAIN)
  42                 return "PCI0";
  43         if (dev->path.type != DEVICE_PATH_PCI)
  44                 return NULL;
  45
  46         switch (dev->path.pci.devfn) {
  47         case EHCI1_DEVFN:
  48                 return "EHC0";
  49         case LPC_DEVFN:
  50                 return "LPCB";
  51         case SATA_DEVFN:
  52                 return "STCR";
  53         case SD_DEVFN:
  54                 return "SDCN";
  55         case SMBUS_DEVFN:
  56                 return "SBUS";
  57         case XHCI_DEVFN:
  58                 return "XHC0";
  59         default:
  60                 return NULL;
  61         }
  62 };
  63
  64 struct device_operations pci_domain_ops = {
  65         .read_resources   = domain_read_resources,
  66         .set_resources    = domain_set_resources,
  67         .enable_resources = domain_enable_resources,
  68         .scan_bus         = pci_domain_scan_bus,
  69         .ops_pci_bus      = pci_bus_default_ops,
  70         .acpi_name        = soc_acpi_name,
  71 };
  72
  73 static void enable_dev(device_t dev)
  74 {
  75         /* Set the operations if it is a special bus type */
  76         if (dev->path.type == DEVICE_PATH_DOMAIN)
  77                 dev->ops = &pci_domain_ops;
  78         else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
  79                 dev->ops = &cpu_bus_ops;
  80         else if (dev->path.type == DEVICE_PATH_PCI)
  81                 sb_enable(dev);
  82 }
  83
  84 static void soc_init(void *chip_info)
  85 {
  86         southbridge_init(chip_info);
  87         setup_bsp_ramtop();
  88 }
  89
  90 static void soc_final(void *chip_info)
  91 {
  92         southbridge_final(chip_info);
  93         fam15_finalize(chip_info);
  94 }
  95
  96 struct chip_operations soc_amd_stoneyridge_ops = {
  97         CHIP_NAME("AMD StoneyRidge SOC")
  98         .enable_dev = &enable_dev,
  99         .init = &soc_init,
 100         .final = &soc_final
 101 };
 102
 103 static void earliest_ramstage(void *unused)
 104 {
 105         post_code(0x46);
 106         if (IS_ENABLED(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW))
 107                 psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW2, "smu_fw2");
 108
 109         post_code(0x47);
 110         do_agesawrapper(agesawrapper_amdinitenv, "amdinitenv");
 111 }
 112
 113 BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, earliest_ramstage, NULL);