crossgcc: Remove "Make"
[coreboot.git] / util / uio_usbdebug / uio_usbdebug_intel.c
blobb6c131c7fc7a30fd98d691c951eae49c933d4f49
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <arch/io.h>
4 #include <device/device.h>
5 #include <device/pci_ehci.h>
6 #include <console/usb.h>
8 extern void *ehci_bar;
10 pci_devfn_t pci_ehci_dbg_dev(unsigned hcd_idx)
12 u32 class;
13 pci_devfn_t dev;
15 #if CONFIG_HAVE_USBDEBUG_OPTIONS
16 if (hcd_idx==2)
17 dev = PCI_DEV(0, 0x1a, 0);
18 else
19 dev = PCI_DEV(0, 0x1d, 0);
20 #else
21 dev = PCI_DEV(0, 0x1d, 7);
22 #endif
24 class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8;
25 #if CONFIG_HAVE_USBDEBUG_OPTIONS
26 if (class != PCI_EHCI_CLASSCODE) {
27 /* If we enter here before RCBA programming, EHCI function may
28 * appear with the highest function number instead.
30 dev |= PCI_DEV(0, 0, 7);
31 class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8;
33 #endif
34 if (class != PCI_EHCI_CLASSCODE)
35 return 0;
37 return dev;
40 void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port)
42 /* claim USB debug port */
43 const unsigned long dbgctl_addr =
44 ((unsigned long)ehci_bar) + CONFIG_EHCI_DEBUG_OFFSET;
45 write32(dbgctl_addr, read32(dbgctl_addr) | (1 << 30));
48 void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base)