src/southbridge/amd/pi/hudson/hudson.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2010 Advanced Micro Devices, Inc.
   5  * Copyright (C) 2014 Sage Electronic Engineering, LLC
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #ifndef HUDSON_H
  18 #define HUDSON_H
  19
  20 #include <types.h>
  21 #include <device/pci_ids.h>
  22 #include <device/device.h>
  23 #include "chip.h"
  24
  25 /* Power management index/data registers */
  26 #define BIOSRAM_INDEX   0xcd4
  27 #define BIOSRAM_DATA    0xcd5
  28 #define PM_INDEX        0xcd6
  29 #define PM_DATA         0xcd7
  30 #define PM2_INDEX       0xcd0
  31 #define PM2_DATA        0xcd1
  32
  33 #define HUDSON_ACPI_IO_BASE 0x800
  34
  35 #define ACPI_PM_EVT_BLK         (HUDSON_ACPI_IO_BASE + 0x00) /* 4 bytes */
  36 #define ACPI_PM1_CNT_BLK        (HUDSON_ACPI_IO_BASE + 0x04) /* 2 bytes */
  37 #define ACPI_PM_TMR_BLK         (HUDSON_ACPI_IO_BASE + 0x18) /* 4 bytes */
  38 #define ACPI_GPE0_BLK           (HUDSON_ACPI_IO_BASE + 0x10) /* 8 bytes */
  39 #define ACPI_CPU_CONTROL        (HUDSON_ACPI_IO_BASE + 0x08) /* 6 bytes */
  40
  41 #define ACPI_SMI_CTL_PORT               0xb2
  42 #define ACPI_SMI_CMD_CST_CONTROL        0xde
  43 #define ACPI_SMI_CMD_PST_CONTROL        0xad
  44 #define ACPI_SMI_CMD_DISABLE            0xbe
  45 #define ACPI_SMI_CMD_ENABLE             0xef
  46 #define ACPI_SMI_CMD_S4_REQ             0xc0
  47
  48 #define REV_HUDSON_A11  0x11
  49 #define REV_HUDSON_A12  0x12
  50
  51 #define SPIROM_BASE_ADDRESS_REGISTER  0xA0
  52 #define SPI_ROM_ENABLE                0x02
  53 #define SPI_BASE_ADDRESS              0xFEC10000
  54
  55 #define LPC_IO_PORT_DECODE_ENABLE     0x44
  56 #define DECODE_ENABLE_PARALLEL_PORT0  BIT(0)
  57 #define DECODE_ENABLE_PARALLEL_PORT1  BIT(1)
  58 #define DECODE_ENABLE_PARALLEL_PORT2  BIT(2)
  59 #define DECODE_ENABLE_PARALLEL_PORT3  BIT(3)
  60 #define DECODE_ENABLE_PARALLEL_PORT4  BIT(4)
  61 #define DECODE_ENABLE_PARALLEL_PORT5  BIT(5)
  62 #define DECODE_ENABLE_SERIAL_PORT0    BIT(6)
  63 #define DECODE_ENABLE_SERIAL_PORT1    BIT(7)
  64 #define DECODE_ENABLE_SERIAL_PORT2    BIT(8)
  65 #define DECODE_ENABLE_SERIAL_PORT3    BIT(9)
  66 #define DECODE_ENABLE_SERIAL_PORT4    BIT(10)
  67 #define DECODE_ENABLE_SERIAL_PORT5    BIT(11)
  68 #define DECODE_ENABLE_SERIAL_PORT6    BIT(12)
  69 #define DECODE_ENABLE_SERIAL_PORT7    BIT(13)
  70 #define DECODE_ENABLE_AUDIO_PORT0     BIT(14)
  71 #define DECODE_ENABLE_AUDIO_PORT1     BIT(15)
  72 #define DECODE_ENABLE_AUDIO_PORT2     BIT(16)
  73 #define DECODE_ENABLE_AUDIO_PORT3     BIT(17)
  74 #define DECODE_ENABLE_MIDI_PORT0      BIT(18)
  75 #define DECODE_ENABLE_MIDI_PORT1      BIT(19)
  76 #define DECODE_ENABLE_MIDI_PORT2      BIT(20)
  77 #define DECODE_ENABLE_MIDI_PORT3      BIT(21)
  78 #define DECODE_ENABLE_MSS_PORT0       BIT(22)
  79 #define DECODE_ENABLE_MSS_PORT1       BIT(23)
  80 #define DECODE_ENABLE_MSS_PORT2       BIT(24)
  81 #define DECODE_ENABLE_MSS_PORT3       BIT(25)
  82 #define DECODE_ENABLE_FDC_PORT0       BIT(26)
  83 #define DECODE_ENABLE_FDC_PORT1       BIT(27)
  84 #define DECODE_ENABLE_GAME_PORT       BIT(28)
  85 #define DECODE_ENABLE_KBC_PORT        BIT(29)
  86 #define DECODE_ENABLE_ACPIUC_PORT     BIT(30)
  87 #define DECODE_ENABLE_ADLIB_PORT      BIT(31)
  88
  89 #define SPI_CNTRL0                    0x00
  90 #define SPI_READ_MODE_MASK            (BIT(30) | BIT(29) | BIT(18))
  91 /* Nominal is 16.7MHz on older devices, 33MHz on newer */
  92 #define SPI_READ_MODE_NOM             0x00000000
  93 #define SPI_READ_MODE_DUAL112         (          BIT(29)          )
  94 #define SPI_READ_MODE_QUAD114         (          BIT(29) | BIT(18))
  95 #define SPI_READ_MODE_DUAL122         (BIT(30)                    )
  96 #define SPI_READ_MODE_QUAD144         (BIT(30) |           BIT(18))
  97 #define SPI_READ_MODE_NORMAL66        (BIT(30) | BIT(29)          )
  98 /* Nominal and SPI_READ_MODE_FAST_HUDSON1 are the only valid choices for H1 */
  99 #define SPI_READ_MODE_FAST_HUDSON1    (                    BIT(18))
 100 #define SPI_READ_MODE_FAST            (BIT(30) | BIT(29) | BIT(18))
 101 #define SPI_ARB_ENABLE                BIT(19)
 102
 103 #define SPI_CNTRL1                    0x0c
 104 /* Use SPI_SPEED_16M-SPI_SPEED_66M below for hudson and bolton */
 105 #define SPI_CNTRL1_SPEED_MASK         (BIT(15) | BIT(14) | BIT(13) | BIT(12))
 106 #define SPI_NORM_SPEED_SH             12
 107 #define SPI_FAST_SPEED_SH             8
 108
 109 #define SPI100_ENABLE                 0x20
 110 #define SPI_USE_SPI100                BIT(0)
 111
 112 #define SPI100_SPEED_CONFIG           0x22
 113 #define SPI_SPEED_66M                 (0x0)
 114 #define SPI_SPEED_33M                 (                  BIT(0))
 115 #define SPI_SPEED_22M                 (         BIT(1)         )
 116 #define SPI_SPEED_16M                 (         BIT(1) | BIT(0))
 117 #define SPI_SPEED_100M                (BIT(2)                  )
 118 #define SPI_SPEED_800K                (BIT(2) |          BIT(0))
 119 #define SPI_NORM_SPEED_NEW_SH         12
 120 #define SPI_FAST_SPEED_NEW_SH         8
 121 #define SPI_ALT_SPEED_NEW_SH          4
 122 #define SPI_TPM_SPEED_NEW_SH          0
 123
 124 #define SPI100_HOST_PREF_CONFIG       0x2c
 125 #define SPI_RD4DW_EN_HOST             BIT(15)
 126
 127 static inline int hudson_sata_enable(void)
 128 {
 129         /* True if IDE or AHCI. */
 130         return (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 2);
 131 }
 132
 133 static inline int hudson_ide_enable(void)
 134 {
 135         /* True if IDE or LEGACY IDE. */
 136         return (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 3);
 137 }
 138
 139 #ifndef __SMM__
 140
 141 void pm_write8(u8 reg, u8 value);
 142 u8 pm_read8(u8 reg);
 143 void pm_write16(u8 reg, u16 value);
 144 u16 pm_read16(u16 reg);
 145
 146 #ifdef __PRE_RAM__
 147 void hudson_lpc_port80(void);
 148 void hudson_lpc_decode(void);
 149 void hudson_pci_port80(void);
 150 void hudson_clk_output_48Mhz(void);
 151 void hudson_read_mode(u32 mode);
 152 void hudson_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm);
 153 void hudson_disable_4dw_burst(void);
 154 void hudson_set_readspeed(u16 norm, u16 fast);
 155
 156 int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);
 157 int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
 158 #if IS_ENABLED(CONFIG_HUDSON_UART)
 159 void configure_hudson_uart(void);
 160 #endif
 161
 162 #else
 163 void hudson_enable(device_t dev);
 164 void s3_resume_init_data(void *FchParams);
 165
 166 #endif /* __PRE_RAM__ */
 167 #endif /* __SMM__ */
 168
 169 #endif /* HUDSON_H */