| blob | db331c9c931309ca9f65b555222e5770525ae262 |
1 /* $NoKeywords:$ */
2 /**
3 * @file
4 *
5 * Install of build options for a combination of package type, processor, and features.
6 *
7 * This file generates the defaults tables for the all platform solution
8 * combinations. The documented build options are imported from a user
9 * controlled file for processing.
10 *
11 * @xrefitem bom "File Content Label" "Release Content"
12 * @e project: AGESA
13 * @e sub-project: Core
14 * @e \$Revision: 60740 $ @e \$Date: 2011-10-20 19:47:10 -0600 (Thu, 20 Oct 2011) $
15 */
16 /*****************************************************************************
17 *
18 * Copyright (C) 2012 Advanced Micro Devices, Inc.
19 * All rights reserved.
20 *
21 * Redistribution and use in source and binary forms, with or without
22 * modification, are permitted provided that the following conditions are met:
23 * * Redistributions of source code must retain the above copyright
24 * notice, this list of conditions and the following disclaimer.
25 * * Redistributions in binary form must reproduce the above copyright
26 * notice, this list of conditions and the following disclaimer in the
27 * documentation and/or other materials provided with the distribution.
28 * * Neither the name of Advanced Micro Devices, Inc. nor the names of
29 * its contributors may be used to endorse or promote products derived
30 * from this software without specific prior written permission.
31 *
32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
34 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
35 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
36 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
39 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
41 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 *
43 *
44 ***************************************************************************/
46 /*****************************************************************************
47 *
48 * Start processing the user options: First, set default settings
49 *
50 ****************************************************************************/
52 /* Available options for image builds.
53 *
54 * As part of the image build for each image, define the options below to select the
55 * AGESA entry points included in that image. Turn these on in your option c file, not
56 * here.
57 */
58 // #define AGESA_ENTRY_INIT_RESET TRUE
59 // #define AGESA_ENTRY_INIT_RECOVERY TRUE
60 // #define AGESA_ENTRY_INIT_EARLY TRUE
61 // #define AGESA_ENTRY_INIT_POST TRUE
62 // #define AGESA_ENTRY_INIT_ENV TRUE
63 // #define AGESA_ENTRY_INIT_MID TRUE
64 // #define AGESA_ENTRY_INIT_LATE TRUE
65 // #define AGESA_ENTRY_INIT_S3SAVE TRUE
66 // #define AGESA_ENTRY_INIT_RESUME TRUE
67 // #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE
68 // #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE
70 /* Defaults for private/internal build control settings */
71 /* Available options for image builds.
72 *
73 * As part of the image build for each image, define the options below to select the
74 * AGESA entry points included in that image.
75 */
77 VOLATILE AMD_MODULE_HEADER mCpuModuleID = {
78 //ModuleHeaderSignature
79 // Remove 'DOM$' as temp solution before update BinUtil.exe ,
81 //ModuleIdentifier[8]
82 AGESA_ID,
83 //ModuleVersion[12]
84 AGESA_VERSION_STRING,
85 //ModuleDispatcher
87 //NextBlock
88 NULL
89 };
91 /* Process user desired AGESA entry points */
92 #ifndef AGESA_ENTRY_INIT_RESET
93 #define AGESA_ENTRY_INIT_RESET FALSE
94 #endif
96 #ifndef AGESA_ENTRY_INIT_RECOVERY
97 #define AGESA_ENTRY_INIT_RECOVERY FALSE
98 #endif
100 #ifndef AGESA_ENTRY_INIT_EARLY
101 #define AGESA_ENTRY_INIT_EARLY FALSE
102 #endif
104 #ifndef AGESA_ENTRY_INIT_POST
105 #define AGESA_ENTRY_INIT_POST FALSE
106 #endif
108 #ifndef AGESA_ENTRY_INIT_ENV
109 #define AGESA_ENTRY_INIT_ENV FALSE
110 #endif
112 #ifndef AGESA_ENTRY_INIT_MID
113 #define AGESA_ENTRY_INIT_MID FALSE
114 #endif
116 #ifndef AGESA_ENTRY_INIT_LATE
117 #define AGESA_ENTRY_INIT_LATE FALSE
118 #endif
120 #ifndef AGESA_ENTRY_INIT_S3SAVE
121 #define AGESA_ENTRY_INIT_S3SAVE FALSE
122 #endif
124 #ifndef AGESA_ENTRY_INIT_RESUME
125 #define AGESA_ENTRY_INIT_RESUME FALSE
126 #endif
128 #ifndef AGESA_ENTRY_INIT_LATE_RESTORE
129 #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE
130 #endif
132 #ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES
133 #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE
134 #endif
136 /* Default the late AP entry point to off. It can be enabled
137 by any family that may need the late AP functionality, or
138 by any feature code that may need it. The IBVs no longer
139 have control over this entry point. */
140 #ifdef AGESA_ENTRY_LATE_RUN_AP_TASK
141 #undef AGESA_ENTRY_LATE_RUN_AP_TASK
142 #endif
143 #define AGESA_ENTRY_LATE_RUN_AP_TASK FALSE
147 /* Process solution defined socket / family installations
148 *
149 * As part of the release package for each image, define the options below to select the
150 * AGESA processor support included in that image.
151 */
153 /* Default sockets to off */
154 #define OPTION_G34_SOCKET_SUPPORT FALSE
155 #define OPTION_C32_SOCKET_SUPPORT FALSE
156 #define OPTION_G2012_SOCKET_SUPPORT FALSE
157 #define OPTION_C2012_SOCKET_SUPPORT FALSE
158 #define OPTION_S1G3_SOCKET_SUPPORT FALSE
159 #define OPTION_S1G4_SOCKET_SUPPORT FALSE
160 #define OPTION_ASB2_SOCKET_SUPPORT FALSE
161 #define OPTION_FS1_SOCKET_SUPPORT FALSE
162 #define OPTION_FM1_SOCKET_SUPPORT FALSE
163 #define OPTION_FM2_SOCKET_SUPPORT FALSE
164 #define OPTION_FP1_SOCKET_SUPPORT FALSE
165 #define OPTION_FP2_SOCKET_SUPPORT FALSE
166 #define OPTION_FT1_SOCKET_SUPPORT FALSE
167 #define OPTION_FT2_SOCKET_SUPPORT FALSE
168 #define OPTION_AM3_SOCKET_SUPPORT FALSE
170 /* Default families to off */
171 #define OPTION_FAMILY10H FALSE
172 #define OPTION_FAMILY12H FALSE
173 #define OPTION_FAMILY14H FALSE
174 #define OPTION_FAMILY15H FALSE
175 #define OPTION_FAMILY15H_MODEL_0x FALSE
176 #define OPTION_FAMILY15H_MODEL_1x FALSE
177 #define OPTION_FAMILY15H_MODEL_2x FALSE
180 /* Enable the appropriate socket support */
181 #ifdef INSTALL_G34_SOCKET_SUPPORT
182 #if INSTALL_G34_SOCKET_SUPPORT == TRUE
183 #undef OPTION_G34_SOCKET_SUPPORT
184 #define OPTION_G34_SOCKET_SUPPORT TRUE
185 #endif
186 #endif
188 #ifdef INSTALL_C32_SOCKET_SUPPORT
189 #if INSTALL_C32_SOCKET_SUPPORT == TRUE
190 #undef OPTION_C32_SOCKET_SUPPORT
191 #define OPTION_C32_SOCKET_SUPPORT TRUE
192 #endif
193 #endif
195 #ifdef INSTALL_G2012_SOCKET_SUPPORT
196 #if INSTALL_G2012_SOCKET_SUPPORT == TRUE
197 #undef OPTION_G2012_SOCKET_SUPPORT
198 #define OPTION_G2012_SOCKET_SUPPORT TRUE
199 #endif
200 #endif
202 #ifdef INSTALL_C2012_SOCKET_SUPPORT
203 #if INSTALL_C2012_SOCKET_SUPPORT == TRUE
204 #undef OPTION_C2012_SOCKET_SUPPORT
205 #define OPTION_C2012_SOCKET_SUPPORT TRUE
206 #endif
207 #endif
209 #ifdef INSTALL_S1G3_SOCKET_SUPPORT
210 #if INSTALL_S1G3_SOCKET_SUPPORT == TRUE
211 #undef OPTION_S1G3_SOCKET_SUPPORT
212 #define OPTION_S1G3_SOCKET_SUPPORT TRUE
213 #endif
214 #endif
216 #ifdef INSTALL_S1G4_SOCKET_SUPPORT
217 #if INSTALL_S1G4_SOCKET_SUPPORT == TRUE
218 #undef OPTION_S1G4_SOCKET_SUPPORT
219 #define OPTION_S1G4_SOCKET_SUPPORT TRUE
220 #endif
221 #endif
223 #ifdef INSTALL_ASB2_SOCKET_SUPPORT
224 #if INSTALL_ASB2_SOCKET_SUPPORT == TRUE
225 #undef OPTION_ASB2_SOCKET_SUPPORT
226 #define OPTION_ASB2_SOCKET_SUPPORT TRUE
227 #endif
228 #endif
230 #ifdef INSTALL_FS1_SOCKET_SUPPORT
231 #if INSTALL_FS1_SOCKET_SUPPORT == TRUE
232 #undef OPTION_FS1_SOCKET_SUPPORT
233 #define OPTION_FS1_SOCKET_SUPPORT TRUE
234 #endif
235 #endif
237 #ifdef INSTALL_FM1_SOCKET_SUPPORT
238 #if INSTALL_FM1_SOCKET_SUPPORT == TRUE
239 #undef OPTION_FM1_SOCKET_SUPPORT
240 #define OPTION_FM1_SOCKET_SUPPORT TRUE
241 #endif
242 #endif
244 #ifdef INSTALL_FM2_SOCKET_SUPPORT
245 #if INSTALL_FM2_SOCKET_SUPPORT == TRUE
246 #undef OPTION_FM2_SOCKET_SUPPORT
247 #define OPTION_FM2_SOCKET_SUPPORT TRUE
248 #endif
249 #endif
251 #ifdef INSTALL_FP1_SOCKET_SUPPORT
252 #if INSTALL_FP1_SOCKET_SUPPORT == TRUE
253 #undef OPTION_FP1_SOCKET_SUPPORT
254 #define OPTION_FP1_SOCKET_SUPPORT TRUE
255 #endif
256 #endif
258 #ifdef INSTALL_FP2_SOCKET_SUPPORT
259 #if INSTALL_FP2_SOCKET_SUPPORT == TRUE
260 #undef OPTION_FP2_SOCKET_SUPPORT
261 #define OPTION_FP2_SOCKET_SUPPORT TRUE
262 #endif
263 #endif
265 #ifdef INSTALL_FT1_SOCKET_SUPPORT
266 #if INSTALL_FT1_SOCKET_SUPPORT == TRUE
267 #undef OPTION_FT1_SOCKET_SUPPORT
268 #define OPTION_FT1_SOCKET_SUPPORT TRUE
269 #endif
270 #endif
272 #ifdef INSTALL_FT2_SOCKET_SUPPORT
273 #if INSTALL_FT2_SOCKET_SUPPORT == TRUE
274 #undef OPTION_FT2_SOCKET_SUPPORT
275 #define OPTION_FT2_SOCKET_SUPPORT TRUE
276 #endif
277 #endif
279 #ifdef INSTALL_AM3_SOCKET_SUPPORT
280 #if INSTALL_AM3_SOCKET_SUPPORT == TRUE
281 #undef OPTION_AM3_SOCKET_SUPPORT
282 #define OPTION_AM3_SOCKET_SUPPORT TRUE
283 #endif
284 #endif
287 /* Enable the appropriate family support */
288 // F10 is supported in G34, C32, S1g4, ASB2, S1g3, & AM3
289 #ifdef INSTALL_FAMILY_10_SUPPORT
290 #if INSTALL_FAMILY_10_SUPPORT == TRUE
291 #undef OPTION_FAMILY10H
292 #define OPTION_FAMILY10H TRUE
293 #endif
294 #endif
296 // F12 is supported in FP1, FS1, & FM1
297 #ifdef INSTALL_FAMILY_12_SUPPORT
298 #if INSTALL_FAMILY_12_SUPPORT == TRUE
299 #undef OPTION_FAMILY12H
300 #define OPTION_FAMILY12H TRUE
301 #endif
302 #endif
304 // F14 is supported in FT1 and FT2
305 #ifdef INSTALL_FAMILY_14_SUPPORT
306 #if INSTALL_FAMILY_14_SUPPORT == TRUE
307 #undef OPTION_FAMILY14H
308 #define OPTION_FAMILY14H TRUE
309 #endif
310 #endif
312 // F15_0x is supported in G34, C32, & AM3
313 #ifdef INSTALL_FAMILY_15_MODEL_0x_SUPPORT
314 #if INSTALL_FAMILY_15_MODEL_0x_SUPPORT == TRUE
315 #undef OPTION_FAMILY15H
316 #define OPTION_FAMILY15H TRUE
317 #undef OPTION_FAMILY15H_MODEL_0x
318 #define OPTION_FAMILY15H_MODEL_0x TRUE
319 #endif
320 #endif
322 // F15_1x is supported in FS1r2, FM2, & FP2
323 #ifdef INSTALL_FAMILY_15_MODEL_1x_SUPPORT
324 #if INSTALL_FAMILY_15_MODEL_1x_SUPPORT == TRUE
325 #undef OPTION_FAMILY15H
326 #define OPTION_FAMILY15H TRUE
327 #undef OPTION_FAMILY15H_MODEL_1x
328 #define OPTION_FAMILY15H_MODEL_1x TRUE
329 #endif
330 #endif
332 // F15_2x is supported in G2012, C2012, & FM2
333 #ifdef INSTALL_FAMILY_15_MODEL_2x_SUPPORT
334 #if INSTALL_FAMILY_15_MODEL_2x_SUPPORT == TRUE
335 #undef OPTION_FAMILY15H
336 #define OPTION_FAMILY15H TRUE
337 #undef OPTION_FAMILY15H_MODEL_2x
338 #define OPTION_FAMILY15H_MODEL_2x TRUE
339 #endif
340 #endif
343 /* Turn off families not required by socket designations */
344 #if (OPTION_FAMILY10H == TRUE)
345 #if (OPTION_G34_SOCKET_SUPPORT == FALSE) && (OPTION_C32_SOCKET_SUPPORT == FALSE) && (OPTION_S1G3_SOCKET_SUPPORT == FALSE) && (OPTION_S1G4_SOCKET_SUPPORT == FALSE) && (OPTION_ASB2_SOCKET_SUPPORT == FALSE) && (OPTION_AM3_SOCKET_SUPPORT == FALSE)
346 #undef OPTION_FAMILY10H
347 #define OPTION_FAMILY10H FALSE
348 #endif
349 #endif
351 #if (OPTION_FAMILY12H == TRUE)
352 #if (OPTION_FS1_SOCKET_SUPPORT == FALSE) && (OPTION_FM1_SOCKET_SUPPORT == FALSE) && (OPTION_FP1_SOCKET_SUPPORT == FALSE)
353 #undef OPTION_FAMILY12H
354 #define OPTION_FAMILY12H FALSE
355 #endif
356 #endif
358 #if (OPTION_FAMILY14H == TRUE)
359 #if (OPTION_FT1_SOCKET_SUPPORT == FALSE) && (OPTION_FT2_SOCKET_SUPPORT == FALSE)
360 #undef OPTION_FAMILY14H
361 #define OPTION_FAMILY14H FALSE
362 #endif
363 #endif
365 #if (OPTION_FAMILY15H_MODEL_0x == TRUE)
366 #if (OPTION_G34_SOCKET_SUPPORT == FALSE) && (OPTION_C32_SOCKET_SUPPORT == FALSE) && (OPTION_AM3_SOCKET_SUPPORT == FALSE)
367 #undef OPTION_FAMILY15H_MODEL_0x
368 #define OPTION_FAMILY15H_MODEL_0x FALSE
369 #endif
370 #endif
372 #if (OPTION_FAMILY15H_MODEL_1x == TRUE)
373 #if (OPTION_FS1_SOCKET_SUPPORT == FALSE) && (OPTION_FM2_SOCKET_SUPPORT == FALSE) && (OPTION_FP2_SOCKET_SUPPORT == FALSE)
374 #undef OPTION_FAMILY15H_MODEL_1x
375 #define OPTION_FAMILY15H_MODEL_1x FALSE
376 #endif
377 #endif
379 #if (OPTION_FAMILY15H_MODEL_2x == TRUE)
380 #if (OPTION_G2012_SOCKET_SUPPORT == FALSE) && (OPTION_C2012_SOCKET_SUPPORT == FALSE) && (OPTION_FM2_SOCKET_SUPPORT == FALSE)
381 #undef OPTION_FAMILY15H_MODEL_2x
382 #define OPTION_FAMILY15H_MODEL_2x FALSE
383 #endif
384 #endif
386 #if (OPTION_FAMILY15H_MODEL_0x == FALSE) && (OPTION_FAMILY15H_MODEL_1x == FALSE) && (OPTION_FAMILY15H_MODEL_2x == FALSE)
387 #undef OPTION_FAMILY15H
388 #define OPTION_FAMILY15H FALSE
389 #endif
391 /* Check for invalid combinations of socket/family */
392 #if (OPTION_G34_SOCKET_SUPPORT == TRUE)
393 #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H_MODEL_0x == FALSE)
394 #error No G34 supported families included in the build
395 #endif
396 #endif
398 #if (OPTION_C32_SOCKET_SUPPORT == TRUE)
399 #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H_MODEL_0x == FALSE)
400 #error No C32 supported families included in the build
401 #endif
402 #endif
404 #if (OPTION_G2012_SOCKET_SUPPORT == TRUE)
405 #if (OPTION_FAMILY15H_MODEL_2x == FALSE)
406 #error No G2012 supported families included in the build
407 #endif
408 #endif
410 #if (OPTION_C2012_SOCKET_SUPPORT == TRUE)
411 #if (OPTION_FAMILY15H_MODEL_2x == FALSE)
412 #error No C2012 supported families included in the build
413 #endif
414 #endif
416 #if (OPTION_S1G3_SOCKET_SUPPORT == TRUE)
417 #if (OPTION_FAMILY10H == FALSE)
418 #error No S1G3 supported families included in the build
419 #endif
420 #endif
422 #if (OPTION_S1G4_SOCKET_SUPPORT == TRUE)
423 #if (OPTION_FAMILY10H == FALSE)
424 #error No S1G4 supported families included in the build
425 #endif
426 #endif
428 #if (OPTION_ASB2_SOCKET_SUPPORT == TRUE)
429 #if (OPTION_FAMILY10H == FALSE)
430 #error No ASB2 supported families included in the build
431 #endif
432 #endif
434 #if (OPTION_FS1_SOCKET_SUPPORT == TRUE)
435 #if (OPTION_FAMILY12H == FALSE) && (OPTION_FAMILY15H_MODEL_1x == FALSE)
436 #error No FS1 supported families included in the build
437 #endif
438 #endif
440 #if (OPTION_FM1_SOCKET_SUPPORT == TRUE)
441 #if (OPTION_FAMILY12H == FALSE)
442 #error No FM1 supported families included in the build
443 #endif
444 #endif
446 #if (OPTION_FM2_SOCKET_SUPPORT == TRUE)
447 #if (OPTION_FAMILY15H_MODEL_1x == FALSE) && (OPTION_FAMILY15H_MODEL_2x == FALSE)
448 #error No FM2 supported families included in the build
449 #endif
450 #endif
452 #if (OPTION_FP1_SOCKET_SUPPORT == TRUE)
453 #if (OPTION_FAMILY12H == FALSE)
454 #error No FP1 supported families included in the build
455 #endif
456 #endif
458 #if (OPTION_FP2_SOCKET_SUPPORT == TRUE)
459 #if (OPTION_FAMILY15H_MODEL_1x == FALSE)
460 #error No FP2 supported families included in the build
461 #endif
462 #endif
464 #if (OPTION_FT1_SOCKET_SUPPORT == TRUE)
465 #if (OPTION_FAMILY14H == FALSE)
466 #error No FT1 supported families included in the build
467 #endif
468 #endif
470 #if (OPTION_FT2_SOCKET_SUPPORT == TRUE)
471 #if (OPTION_FAMILY14H == FALSE)
472 #error No FT2 supported families included in the build
473 #endif
474 #endif
476 #if (OPTION_AM3_SOCKET_SUPPORT == TRUE)
477 #if (OPTION_FAMILY10H == FALSE) && (OPTION_FAMILY15H_MODEL_0x == FALSE)
478 #error No AM3 supported families included in the build
479 #endif
480 #endif
483 /* Process AGESA private data
484 *
485 * Turn on appropriate CPU models and memory controllers,
486 * as well as some other memory controls.
487 */
489 /* Default all models to off */
490 #define OPTION_FAMILY10H_BL FALSE
491 #define OPTION_FAMILY10H_DA FALSE
492 #define OPTION_FAMILY10H_HY FALSE
493 #define OPTION_FAMILY10H_PH FALSE
494 #define OPTION_FAMILY10H_RB FALSE
495 #define OPTION_FAMILY12H_LN FALSE
496 #define OPTION_FAMILY14H_ON FALSE
497 #define OPTION_FAMILY14H_KR FALSE
498 #define OPTION_FAMILY15H_OR FALSE
499 #define OPTION_FAMILY15H_TN FALSE
500 #define OPTION_FAMILY15H_KM FALSE
502 /* Default all memory controllers to off */
503 #define OPTION_MEMCTLR_DR FALSE
504 #define OPTION_MEMCTLR_HY FALSE
505 #define OPTION_MEMCTLR_OR FALSE
506 #define OPTION_MEMCTLR_C32 FALSE
507 #define OPTION_MEMCTLR_DA FALSE
508 #define OPTION_MEMCTLR_LN FALSE
509 #define OPTION_MEMCTLR_ON FALSE
510 #define OPTION_MEMCTLR_KR FALSE
511 #define OPTION_MEMCTLR_Ni FALSE
512 #define OPTION_MEMCTLR_PH FALSE
513 #define OPTION_MEMCTLR_RB FALSE
514 #define OPTION_MEMCTLR_TN FALSE
515 #define OPTION_MEMCTLR_KM FALSE
517 /* Default all memory controls to off */
518 #define OPTION_HW_WRITE_LEV_TRAINING FALSE
519 #define OPTION_SW_WRITE_LEV_TRAINING FALSE
520 #define OPTION_CONTINOUS_PATTERN_GENERATION FALSE
521 #define OPTION_HW_DQS_REC_EN_TRAINING FALSE
522 #define OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING FALSE
523 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING FALSE
524 #define OPTION_NON_OPT_SW_RD_WR_POS_TRAINING FALSE
525 #define OPTION_OPT_SW_RD_WR_POS_TRAINING FALSE
526 #define OPTION_MAX_RD_LAT_TRAINING FALSE
527 #define OPTION_HW_DRAM_INIT FALSE
528 #define OPTION_SW_DRAM_INIT FALSE
529 #define OPTION_S3_MEM_SUPPORT FALSE
530 #define OPTION_ADDR_TO_CS_TRANSLATOR FALSE
531 #define OPTION_HW_DQS_REC_EN_SEED_TRAINING FALSE
532 #define OPTION_RDDQS____TRAINING FALSE
534 /* Defaults for public user options */
535 #define OPTION_UDIMMS FALSE
536 #define OPTION_RDIMMS FALSE
537 #define OPTION_SODIMMS FALSE
538 #define OPTION_LRDIMMS FALSE
539 #define OPTION_DDR2 FALSE
540 #define OPTION_DDR3 FALSE
541 #define OPTION_ECC FALSE
542 #define OPTION_BANK_INTERLEAVE FALSE
543 #define OPTION_DCT_INTERLEAVE FALSE
544 #define OPTION_NODE_INTERLEAVE FALSE
545 #define OPTION_PARALLEL_TRAINING FALSE
546 #define OPTION_ONLINE_SPARE FALSE
547 #define OPTION_MEM_RESTORE FALSE
548 #define OPTION_DIMM_EXCLUDE FALSE
550 /* Default all CPU controls to off */
551 #define OPTION_MULTISOCKET FALSE
552 #define OPTION_SRAT FALSE
553 #define OPTION_SLIT FALSE
554 #define OPTION_HT_ASSIST FALSE
555 #define OPTION_ATM_MODE FALSE
556 #define OPTION_CPU_CORELEVLING FALSE
557 #define OPTION_MSG_BASED_C1E FALSE
558 #define OPTION_CPU_CFOH FALSE
559 #define OPTION_C6_STATE FALSE
560 #define OPTION_IO_CSTATE FALSE
561 #define OPTION_CPB FALSE
562 #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT FALSE
563 #define OPTION_CPU_PSTATE_HPC_MODE FALSE
564 #define OPTION_CPU_APM FALSE
565 #define OPTION_S3SCRIPT FALSE
566 #define OPTION_GFX_RECOVERY FALSE
568 /* Default FCH controls to off */
569 #define FCH_SUPPORT FALSE
571 /* Enable all private controls based on socket/family enables */
572 #if (OPTION_G34_SOCKET_SUPPORT == TRUE)
573 #if (OPTION_FAMILY10H == TRUE)
574 #undef OPTION_FAMILY10H_HY
575 #define OPTION_FAMILY10H_HY TRUE
576 #undef OPTION_MEMCTLR_HY
577 #define OPTION_MEMCTLR_HY TRUE
578 #undef OPTION_HW_WRITE_LEV_TRAINING
579 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
580 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
581 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
582 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
583 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
584 #undef OPTION_MAX_RD_LAT_TRAINING
585 #define OPTION_MAX_RD_LAT_TRAINING TRUE
586 #undef OPTION_SW_DRAM_INIT
587 #define OPTION_SW_DRAM_INIT TRUE
588 #undef OPTION_S3_MEM_SUPPORT
589 #define OPTION_S3_MEM_SUPPORT TRUE
590 #undef OPTION_MULTISOCKET
591 #define OPTION_MULTISOCKET TRUE
592 #undef OPTION_SRAT
593 #define OPTION_SRAT TRUE
594 #undef OPTION_SLIT
595 #define OPTION_SLIT TRUE
596 #undef OPTION_HT_ASSIST
597 #define OPTION_HT_ASSIST TRUE
598 #undef OPTION_CPU_CORELEVLING
599 #define OPTION_CPU_CORELEVLING TRUE
600 #undef OPTION_MSG_BASED_C1E
601 #define OPTION_MSG_BASED_C1E TRUE
602 #undef OPTION_CPU_CFOH
603 #define OPTION_CPU_CFOH TRUE
604 #undef OPTION_UDIMMS
605 #define OPTION_UDIMMS TRUE
606 #undef OPTION_RDIMMS
607 #define OPTION_RDIMMS TRUE
608 #undef OPTION_SODIMMS
609 #define OPTION_SODIMMS TRUE
610 #undef OPTION_DDR3
611 #define OPTION_DDR3 TRUE
612 #undef OPTION_ECC
613 #define OPTION_ECC TRUE
614 #undef OPTION_BANK_INTERLEAVE
615 #define OPTION_BANK_INTERLEAVE TRUE
616 #undef OPTION_DCT_INTERLEAVE
617 #define OPTION_DCT_INTERLEAVE TRUE
618 #undef OPTION_NODE_INTERLEAVE
619 #define OPTION_NODE_INTERLEAVE TRUE
620 #undef OPTION_PARALLEL_TRAINING
621 #define OPTION_PARALLEL_TRAINING TRUE
622 #undef OPTION_MEM_RESTORE
623 #define OPTION_MEM_RESTORE TRUE
624 #undef OPTION_ONLINE_SPARE
625 #define OPTION_ONLINE_SPARE TRUE
626 #undef OPTION_DIMM_EXCLUDE
627 #define OPTION_DIMM_EXCLUDE TRUE
628 #endif
629 #if (OPTION_FAMILY15H_MODEL_0x == TRUE)
630 #undef OPTION_FAMILY15H_OR
631 #define OPTION_FAMILY15H_OR TRUE
632 #undef OPTION_MEMCTLR_OR
633 #define OPTION_MEMCTLR_OR TRUE
634 #undef OPTION_HW_WRITE_LEV_TRAINING
635 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
636 #undef OPTION_CONTINOUS_PATTERN_GENERATION
637 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
638 #undef OPTION_HW_DQS_REC_EN_TRAINING
639 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
640 #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
641 #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE
642 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
643 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
644 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
645 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
646 #undef OPTION_MAX_RD_LAT_TRAINING
647 #define OPTION_MAX_RD_LAT_TRAINING TRUE
648 #undef OPTION_SW_DRAM_INIT
649 #define OPTION_SW_DRAM_INIT TRUE
650 #undef OPTION_S3_MEM_SUPPORT
651 #define OPTION_S3_MEM_SUPPORT TRUE
652 #undef OPTION_MULTISOCKET
653 #define OPTION_MULTISOCKET TRUE
654 #undef OPTION_C6_STATE
655 #define OPTION_C6_STATE TRUE
656 #undef OPTION_IO_CSTATE
657 #define OPTION_IO_CSTATE TRUE
658 #undef OPTION_CPB
659 #define OPTION_CPB TRUE
660 #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
661 #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE
662 #undef OPTION_CPU_APM
663 #define OPTION_CPU_APM TRUE
664 #undef OPTION_SRAT
665 #define OPTION_SRAT TRUE
666 #undef OPTION_SLIT
667 #define OPTION_SLIT TRUE
668 #undef OPTION_HT_ASSIST
669 #define OPTION_HT_ASSIST TRUE
670 #undef OPTION_ATM_MODE
671 #define OPTION_ATM_MODE TRUE
672 #undef OPTION_CPU_CORELEVLING
673 #define OPTION_CPU_CORELEVLING TRUE
674 #undef OPTION_MSG_BASED_C1E
675 #define OPTION_MSG_BASED_C1E TRUE
676 #undef OPTION_CPU_CFOH
677 #define OPTION_CPU_CFOH TRUE
678 #undef OPTION_UDIMMS
679 #define OPTION_UDIMMS TRUE
680 #undef OPTION_RDIMMS
681 #define OPTION_RDIMMS TRUE
682 #undef OPTION_SODIMMS
683 #define OPTION_SODIMMS TRUE
684 #undef OPTION_LRDIMMS
685 #define OPTION_LRDIMMS TRUE
686 #undef OPTION_DDR3
687 #define OPTION_DDR3 TRUE
688 #undef OPTION_ECC
689 #define OPTION_ECC TRUE
690 #undef OPTION_BANK_INTERLEAVE
691 #define OPTION_BANK_INTERLEAVE TRUE
692 #undef OPTION_DCT_INTERLEAVE
693 #define OPTION_DCT_INTERLEAVE TRUE
694 #undef OPTION_NODE_INTERLEAVE
695 #define OPTION_NODE_INTERLEAVE TRUE
696 #undef OPTION_MEM_RESTORE
697 #define OPTION_MEM_RESTORE TRUE
698 #undef OPTION_ONLINE_SPARE
699 #define OPTION_ONLINE_SPARE TRUE
700 #undef OPTION_DIMM_EXCLUDE
701 #define OPTION_DIMM_EXCLUDE TRUE
702 #endif
703 #endif
705 #if (OPTION_C32_SOCKET_SUPPORT == TRUE)
706 #if (OPTION_FAMILY10H == TRUE)
707 #undef OPTION_FAMILY10H_HY
708 #define OPTION_FAMILY10H_HY TRUE
709 #undef OPTION_MEMCTLR_C32
710 #define OPTION_MEMCTLR_C32 TRUE
711 #undef OPTION_HW_WRITE_LEV_TRAINING
712 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
713 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
714 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
715 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
716 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
717 #undef OPTION_MAX_RD_LAT_TRAINING
718 #define OPTION_MAX_RD_LAT_TRAINING TRUE
719 #undef OPTION_SW_DRAM_INIT
720 #define OPTION_SW_DRAM_INIT TRUE
721 #undef OPTION_S3_MEM_SUPPORT
722 #define OPTION_S3_MEM_SUPPORT TRUE
723 #undef OPTION_ADDR_TO_CS_TRANSLATOR
724 #define OPTION_ADDR_TO_CS_TRANSLATOR FALSE
725 #undef OPTION_MULTISOCKET
726 #define OPTION_MULTISOCKET TRUE
727 #undef OPTION_SRAT
728 #define OPTION_SRAT TRUE
729 #undef OPTION_SLIT
730 #define OPTION_SLIT TRUE
731 #undef OPTION_HT_ASSIST
732 #define OPTION_HT_ASSIST TRUE
733 #undef OPTION_CPU_CORELEVLING
734 #define OPTION_CPU_CORELEVLING TRUE
735 #undef OPTION_MSG_BASED_C1E
736 #define OPTION_MSG_BASED_C1E TRUE
737 #undef OPTION_CPU_CFOH
738 #define OPTION_CPU_CFOH TRUE
739 #undef OPTION_UDIMMS
740 #define OPTION_UDIMMS TRUE
741 #undef OPTION_RDIMMS
742 #define OPTION_RDIMMS TRUE
743 #undef OPTION_SODIMMS
744 #define OPTION_SODIMMS TRUE
745 #undef OPTION_DDR3
746 #define OPTION_DDR3 TRUE
747 #undef OPTION_ECC
748 #define OPTION_ECC TRUE
749 #undef OPTION_BANK_INTERLEAVE
750 #define OPTION_BANK_INTERLEAVE TRUE
751 #undef OPTION_DCT_INTERLEAVE
752 #define OPTION_DCT_INTERLEAVE TRUE
753 #undef OPTION_NODE_INTERLEAVE
754 #define OPTION_NODE_INTERLEAVE TRUE
755 #undef OPTION_PARALLEL_TRAINING
756 #define OPTION_PARALLEL_TRAINING TRUE
757 #undef OPTION_MEM_RESTORE
758 #define OPTION_MEM_RESTORE TRUE
759 #undef OPTION_ONLINE_SPARE
760 #define OPTION_ONLINE_SPARE TRUE
761 #undef OPTION_DIMM_EXCLUDE
762 #define OPTION_DIMM_EXCLUDE TRUE
763 #endif
764 #if (OPTION_FAMILY15H_MODEL_0x == TRUE)
765 #undef OPTION_FAMILY15H_OR
766 #define OPTION_FAMILY15H_OR TRUE
767 #undef OPTION_MEMCTLR_OR
768 #define OPTION_MEMCTLR_OR TRUE
769 #undef OPTION_HW_WRITE_LEV_TRAINING
770 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
771 #undef OPTION_CONTINOUS_PATTERN_GENERATION
772 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
773 #undef OPTION_HW_DQS_REC_EN_TRAINING
774 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
775 #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
776 #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE
777 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
778 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
779 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
780 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
781 #undef OPTION_MAX_RD_LAT_TRAINING
782 #define OPTION_MAX_RD_LAT_TRAINING TRUE
783 #undef OPTION_SW_DRAM_INIT
784 #define OPTION_SW_DRAM_INIT TRUE
785 #undef OPTION_S3_MEM_SUPPORT
786 #define OPTION_S3_MEM_SUPPORT TRUE
787 #undef OPTION_ADDR_TO_CS_TRANSLATOR
788 #define OPTION_ADDR_TO_CS_TRANSLATOR TRUE
789 #undef OPTION_MULTISOCKET
790 #define OPTION_MULTISOCKET TRUE
791 #undef OPTION_C6_STATE
792 #define OPTION_C6_STATE TRUE
793 #undef OPTION_IO_CSTATE
794 #define OPTION_IO_CSTATE TRUE
795 #undef OPTION_CPB
796 #define OPTION_CPB TRUE
797 #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
798 #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT TRUE
799 #undef OPTION_CPU_APM
800 #define OPTION_CPU_APM TRUE
801 #undef OPTION_SRAT
802 #define OPTION_SRAT TRUE
803 #undef OPTION_SLIT
804 #define OPTION_SLIT TRUE
805 #undef OPTION_HT_ASSIST
806 #define OPTION_HT_ASSIST TRUE
807 #undef OPTION_ATM_MODE
808 #define OPTION_ATM_MODE TRUE
809 #undef OPTION_CPU_CORELEVLING
810 #define OPTION_CPU_CORELEVLING TRUE
811 #undef OPTION_MSG_BASED_C1E
812 #define OPTION_MSG_BASED_C1E TRUE
813 #undef OPTION_CPU_CFOH
814 #define OPTION_CPU_CFOH TRUE
815 #undef OPTION_UDIMMS
816 #define OPTION_UDIMMS TRUE
817 #undef OPTION_RDIMMS
818 #define OPTION_RDIMMS TRUE
819 #undef OPTION_SODIMMS
820 #define OPTION_SODIMMS TRUE
821 #undef OPTION_LRDIMMS
822 #define OPTION_LRDIMMS TRUE
823 #undef OPTION_DDR3
824 #define OPTION_DDR3 TRUE
825 #undef OPTION_ECC
826 #define OPTION_ECC TRUE
827 #undef OPTION_BANK_INTERLEAVE
828 #define OPTION_BANK_INTERLEAVE TRUE
829 #undef OPTION_DCT_INTERLEAVE
830 #define OPTION_DCT_INTERLEAVE TRUE
831 #undef OPTION_NODE_INTERLEAVE
832 #define OPTION_NODE_INTERLEAVE TRUE
833 #undef OPTION_MEM_RESTORE
834 #define OPTION_MEM_RESTORE TRUE
835 #undef OPTION_ONLINE_SPARE
836 #define OPTION_ONLINE_SPARE TRUE
837 #undef OPTION_DIMM_EXCLUDE
838 #define OPTION_DIMM_EXCLUDE TRUE
839 #endif
840 #endif
842 #if (OPTION_S1G3_SOCKET_SUPPORT == TRUE)
843 #if (OPTION_FAMILY10H == TRUE)
844 #undef OPTION_FAMILY10H_BL
845 #define OPTION_FAMILY10H_BL TRUE
846 #undef OPTION_FAMILY10H_DA
847 #define OPTION_FAMILY10H_DA TRUE
848 #undef OPTION_MEMCTLR_DA
849 #define OPTION_MEMCTLR_DA TRUE
850 #undef OPTION_HW_WRITE_LEV_TRAINING
851 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
852 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
853 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
854 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
855 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
856 #undef OPTION_MAX_RD_LAT_TRAINING
857 #define OPTION_MAX_RD_LAT_TRAINING TRUE
858 #undef OPTION_SW_DRAM_INIT
859 #define OPTION_SW_DRAM_INIT TRUE
860 #undef OPTION_S3_MEM_SUPPORT
861 #define OPTION_S3_MEM_SUPPORT TRUE
862 #undef OPTION_CPU_CORELEVLING
863 #define OPTION_CPU_CORELEVLING TRUE
864 #undef OPTION_CPU_CFOH
865 #define OPTION_CPU_CFOH TRUE
866 #undef OPTION_UDIMMS
867 #define OPTION_UDIMMS TRUE
868 #undef OPTION_SODIMMS
869 #define OPTION_SODIMMS TRUE
870 #undef OPTION_DDR3
871 #define OPTION_DDR3 TRUE
872 #undef OPTION_ECC
873 #define OPTION_ECC TRUE
874 #undef OPTION_BANK_INTERLEAVE
875 #define OPTION_BANK_INTERLEAVE TRUE
876 #undef OPTION_DCT_INTERLEAVE
877 #define OPTION_DCT_INTERLEAVE TRUE
878 #undef OPTION_NODE_INTERLEAVE
879 #define OPTION_NODE_INTERLEAVE TRUE
880 #undef OPTION_PARALLEL_TRAINING
881 #define OPTION_PARALLEL_TRAINING TRUE
882 #undef OPTION_MEM_RESTORE
883 #define OPTION_MEM_RESTORE TRUE
884 #undef OPTION_ONLINE_SPARE
885 #define OPTION_ONLINE_SPARE TRUE
886 #undef OPTION_DIMM_EXCLUDE
887 #define OPTION_DIMM_EXCLUDE TRUE
888 #endif
889 #endif
891 #if (OPTION_S1G4_SOCKET_SUPPORT == TRUE)
892 #if (OPTION_FAMILY10H == TRUE)
893 #undef OPTION_FAMILY10H_BL
894 #define OPTION_FAMILY10H_BL TRUE
895 #undef OPTION_FAMILY10H_DA
896 #define OPTION_FAMILY10H_DA TRUE
897 #undef OPTION_MEMCTLR_DA
898 #define OPTION_MEMCTLR_DA TRUE
899 #undef OPTION_HW_WRITE_LEV_TRAINING
900 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
901 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
902 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
903 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
904 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
905 #undef OPTION_MAX_RD_LAT_TRAINING
906 #define OPTION_MAX_RD_LAT_TRAINING TRUE
907 #undef OPTION_SW_DRAM_INIT
908 #define OPTION_SW_DRAM_INIT TRUE
909 #undef OPTION_S3_MEM_SUPPORT
910 #define OPTION_S3_MEM_SUPPORT TRUE
911 #undef OPTION_CPU_CORELEVLING
912 #define OPTION_CPU_CORELEVLING TRUE
913 #undef OPTION_CPU_CFOH
914 #define OPTION_CPU_CFOH TRUE
915 #undef OPTION_UDIMMS
916 #define OPTION_UDIMMS TRUE
917 #undef OPTION_SODIMMS
918 #define OPTION_SODIMMS TRUE
919 #undef OPTION_DDR3
920 #define OPTION_DDR3 TRUE
921 #undef OPTION_ECC
922 #define OPTION_ECC TRUE
923 #undef OPTION_BANK_INTERLEAVE
924 #define OPTION_BANK_INTERLEAVE TRUE
925 #undef OPTION_DCT_INTERLEAVE
926 #define OPTION_DCT_INTERLEAVE TRUE
927 #undef OPTION_NODE_INTERLEAVE
928 #define OPTION_NODE_INTERLEAVE TRUE
929 #undef OPTION_MEM_RESTORE
930 #define OPTION_MEM_RESTORE TRUE
931 #undef OPTION_DIMM_EXCLUDE
932 #define OPTION_DIMM_EXCLUDE TRUE
933 #endif
934 #endif
936 #if (OPTION_ASB2_SOCKET_SUPPORT == TRUE)
937 #if (OPTION_FAMILY10H == TRUE)
938 #undef OPTION_FAMILY10H_BL
939 #define OPTION_FAMILY10H_BL TRUE
940 #undef OPTION_FAMILY10H_DA
941 #define OPTION_FAMILY10H_DA TRUE
942 #undef OPTION_MEMCTLR_Ni
943 #define OPTION_MEMCTLR_Ni TRUE
944 #undef OPTION_HW_WRITE_LEV_TRAINING
945 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
946 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
947 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
948 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
949 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
950 #undef OPTION_MAX_RD_LAT_TRAINING
951 #define OPTION_MAX_RD_LAT_TRAINING TRUE
952 #undef OPTION_SW_DRAM_INIT
953 #define OPTION_SW_DRAM_INIT TRUE
954 #undef OPTION_S3_MEM_SUPPORT
955 #define OPTION_S3_MEM_SUPPORT TRUE
956 #undef OPTION_CPU_CORELEVLING
957 #define OPTION_CPU_CORELEVLING TRUE
958 #undef OPTION_CPU_CFOH
959 #define OPTION_CPU_CFOH TRUE
960 #undef OPTION_UDIMMS
961 #define OPTION_UDIMMS TRUE
962 #undef OPTION_SODIMMS
963 #define OPTION_SODIMMS TRUE
964 #undef OPTION_DDR3
965 #define OPTION_DDR3 TRUE
966 #undef OPTION_ECC
967 #define OPTION_ECC TRUE
968 #undef OPTION_BANK_INTERLEAVE
969 #define OPTION_BANK_INTERLEAVE TRUE
970 #undef OPTION_DCT_INTERLEAVE
971 #define OPTION_DCT_INTERLEAVE TRUE
972 #undef OPTION_NODE_INTERLEAVE
973 #define OPTION_NODE_INTERLEAVE TRUE
974 #undef OPTION_MEM_RESTORE
975 #define OPTION_MEM_RESTORE TRUE
976 #undef OPTION_DIMM_EXCLUDE
977 #define OPTION_DIMM_EXCLUDE TRUE
978 #endif
979 #endif
981 #if (OPTION_AM3_SOCKET_SUPPORT == TRUE)
982 #if (OPTION_FAMILY10H == TRUE)
983 #undef OPTION_FAMILY10H_BL
984 #define OPTION_FAMILY10H_BL TRUE
985 #undef OPTION_FAMILY10H_DA
986 #define OPTION_FAMILY10H_DA TRUE
987 #undef OPTION_FAMILY10H_PH
988 #define OPTION_FAMILY10H_PH TRUE
989 #undef OPTION_FAMILY10H_RB
990 #define OPTION_FAMILY10H_RB TRUE
991 #undef OPTION_MEMCTLR_RB
992 #define OPTION_MEMCTLR_RB TRUE
993 #undef OPTION_MEMCTLR_DA
994 #define OPTION_MEMCTLR_DA TRUE
995 #undef OPTION_MEMCTLR_PH
996 #define OPTION_MEMCTLR_PH TRUE
997 #undef OPTION_HW_WRITE_LEV_TRAINING
998 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
999 #undef OPTION_OPT_SW_DQS_REC_EN_TRAINING
1000 #define OPTION_OPT_SW_DQS_REC_EN_TRAINING TRUE
1001 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
1002 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
1003 #undef OPTION_MAX_RD_LAT_TRAINING
1004 #define OPTION_MAX_RD_LAT_TRAINING TRUE
1005 #undef OPTION_SW_DRAM_INIT
1006 #define OPTION_SW_DRAM_INIT TRUE
1007 #undef OPTION_S3_MEM_SUPPORT
1008 #define OPTION_S3_MEM_SUPPORT TRUE
1009 #undef OPTION_CPU_CORELEVLING
1010 #define OPTION_CPU_CORELEVLING TRUE
1011 #undef OPTION_CPU_CFOH
1012 #define OPTION_CPU_CFOH TRUE
1013 #undef OPTION_IO_CSTATE
1014 #define OPTION_IO_CSTATE TRUE
1015 #undef OPTION_CPB
1016 #define OPTION_CPB TRUE
1017 #undef OPTION_UDIMMS
1018 #define OPTION_UDIMMS TRUE
1019 #undef OPTION_SODIMMS
1020 #define OPTION_SODIMMS TRUE
1021 #undef OPTION_DDR3
1022 #define OPTION_DDR3 TRUE
1023 #undef OPTION_ECC
1024 #define OPTION_ECC TRUE
1025 #undef OPTION_BANK_INTERLEAVE
1026 #define OPTION_BANK_INTERLEAVE TRUE
1027 #undef OPTION_DCT_INTERLEAVE
1028 #define OPTION_DCT_INTERLEAVE TRUE
1029 #undef OPTION_NODE_INTERLEAVE
1030 #define OPTION_NODE_INTERLEAVE TRUE
1031 #undef OPTION_PARALLEL_TRAINING
1032 #define OPTION_PARALLEL_TRAINING TRUE
1033 #undef OPTION_MEM_RESTORE
1034 #define OPTION_MEM_RESTORE TRUE
1035 #undef OPTION_ONLINE_SPARE
1036 #define OPTION_ONLINE_SPARE TRUE
1037 #undef OPTION_DIMM_EXCLUDE
1038 #define OPTION_DIMM_EXCLUDE TRUE
1039 #endif
1040 #if (OPTION_FAMILY15H_MODEL_0x == TRUE)
1041 #undef OPTION_FAMILY15H_OR
1042 #define OPTION_FAMILY15H_OR TRUE
1043 #undef OPTION_MEMCTLR_OR
1044 #define OPTION_MEMCTLR_OR TRUE
1045 #undef OPTION_HW_WRITE_LEV_TRAINING
1046 #define OPTION_HW_WRITE_LEV_TRAINING TRUE
1047 #undef OPTION_CONTINOUS_PATTERN_GENERATION
1048 #define OPTION_CONTINOUS_PATTERN_GENERATION TRUE
1049 #undef OPTION_HW_DQS_REC_EN_TRAINING
1050 #define OPTION_HW_DQS_REC_EN_TRAINING TRUE
1051 #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
1052 #define OPTION_HW_DQS_REC_EN_SEED_TRAINING TRUE
1053 #undef OPTION_OPT_SW_RD_WR_POS_TRAINING
1054 #define OPTION_OPT_SW_RD_WR_POS_TRAINING TRUE
1055 #undef OPTION_MAX_RD_LAT_TRAINING
1056 #define OPTION_MAX_RD_LAT_TRAINING TRUE
1057 #undef OPTION_SW_DRAM_INIT
1058 #define OPTION_SW_DRAM_INIT TRUE
1059 #undef OPTION_C6_STATE
1060 #define OPTION_C6_STATE TRUE
1061 #undef OPTION_IO_CSTATE
1062 #define OPTION_IO_CSTATE TRUE
1063 #undef OPTION_CPB
1064 #define OPTION_CPB TRUE
1065 #undef OPTION_CPU_APM
1066 #define OPTION_CPU_APM TRUE
1067 #undef OPTION_S3_MEM_SUPPORT
1068 #define OPTION_S3_MEM_SUPPORT TRUE
1069 #undef OPTION_ADDR_TO_CS_TRANSLATOR
1070 #define OPTION_ADDR_TO_CS_TRANSLATOR TRUE
1071 #undef OPTION_ATM_MODE
1072 #define OPTION_ATM_MODE TRUE
1073 #undef OPTION_CPU_CORELEVLING
1074 #define OPTION_CPU_CORELEVLING TRUE
1075 #undef OPTION_CPU_CFOH
1076 #define OPTION_CPU_CFOH TRUE
1077 #undef OPTION_MSG_BASED_C1E
1078 #define OPTION_MSG_BASED_C1E TRUE
1079 #undef OPTION_UDIMMS
1080 #define OPTION_UDIMMS TRUE
1081 #undef OPTION_RDIMMS
1082 #define OPTION_RDIMMS TRUE
1083 #undef OPTION_LRDIMMS
1084 #define OPTION_LRDIMMS TRUE
1085 #undef OPTION_SODIMMS
1086 #define OPTION_SODIMMS TRUE
1087 #undef OPTION_DDR3
1088 #define OPTION_DDR3 TRUE
1089 #undef OPTION_ECC
1090 #define OPTION_ECC TRUE
1091 #undef OPTION_BANK_INTERLEAVE
1092 #define OPTION_BANK_INTERLEAVE TRUE
1093 #undef OPTION_DCT_INTERLEAVE
1094 #define OPTION_DCT_INTERLEAVE TRUE
1095 #undef OPTION_NODE_INTERLEAVE
1096 #define OPTION_NODE_INTERLEAVE TRUE
1097 #undef OPTION_MEM_RESTORE
1098 #define OPTION_MEM_RESTORE TRUE
1099 #undef OPTION_ONLINE_SPARE
1100 #define OPTION_ONLINE_SPARE TRUE
1101 #undef OPTION_DIMM_EXCLUDE
1102 #define OPTION_DIMM_EXCLUDE TRUE
1103 #endif
1104 #endif
1106 #define OPTION_ACPI_PSTATES TRUE
1107 #define OPTION_WHEA TRUE
1108 #define OPTION_DMI TRUE
1109 #define OPTION_EARLY_SAMPLES FALSE
1110 #define CFG_ACPI_PSTATES_PPC TRUE
1111 #define CFG_ACPI_PSTATES_PCT TRUE
1112 #define CFG_ACPI_PSTATES_PSD TRUE
1113 #define CFG_ACPI_PSTATES_PSS TRUE
1114 #define CFG_ACPI_PSTATES_XPSS TRUE
1115 #define CFG_ACPI_PSTATE_PSD_INDPX FALSE
1116 #define CFG_VRM_HIGH_SPEED_ENABLE FALSE
1117 #define CFG_VRM_NB_HIGH_SPEED_ENABLE FALSE
1118 #define OPTION_ALIB TRUE
1119 /*---------------------------------------------------------------------------
1120 * Processing the options: Second, process the user's selections
1121 *--------------------------------------------------------------------------*/
1122 #ifdef BLDOPT_REMOVE_MULTISOCKET_SUPPORT
1123 #if BLDOPT_REMOVE_MULTISOCKET_SUPPORT == TRUE
1124 #undef OPTION_MULTISOCKET
1125 #define OPTION_MULTISOCKET FALSE
1126 #endif
1127 #endif
1128 #ifdef BLDOPT_REMOVE_ECC_SUPPORT
1129 #if BLDOPT_REMOVE_ECC_SUPPORT == TRUE
1130 #undef OPTION_ECC
1131 #define OPTION_ECC FALSE
1132 #endif
1133 #endif
1134 #ifdef BLDOPT_REMOVE_UDIMMS_SUPPORT
1135 #if BLDOPT_REMOVE_UDIMMS_SUPPORT == TRUE
1136 #undef OPTION_UDIMMS
1137 #define OPTION_UDIMMS FALSE
1138 #endif
1139 #endif
1140 #ifdef BLDOPT_REMOVE_RDIMMS_SUPPORT
1141 #if BLDOPT_REMOVE_RDIMMS_SUPPORT == TRUE
1142 #undef OPTION_RDIMMS
1143 #define OPTION_RDIMMS FALSE
1144 #endif
1145 #endif
1146 #ifdef BLDOPT_REMOVE_SODIMMS_SUPPORT
1147 #if BLDOPT_REMOVE_SODIMMS_SUPPORT == TRUE
1148 #undef OPTION_SODIMMS
1149 #define OPTION_SODIMMS FALSE
1150 #endif
1151 #endif
1152 #ifdef BLDOPT_REMOVE_LRDIMMS_SUPPORT
1153 #if BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE
1154 #undef OPTION_LRDIMMS
1155 #define OPTION_LRDIMMS FALSE
1156 #endif
1157 #endif
1158 #ifdef BLDOPT_REMOVE_BANK_INTERLEAVE
1159 #if BLDOPT_REMOVE_BANK_INTERLEAVE == TRUE
1160 #undef OPTION_BANK_INTERLEAVE
1161 #define OPTION_BANK_INTERLEAVE FALSE
1162 #endif
1163 #endif
1164 #ifdef BLDOPT_REMOVE_DCT_INTERLEAVE
1165 #if BLDOPT_REMOVE_DCT_INTERLEAVE == TRUE
1166 #undef OPTION_DCT_INTERLEAVE
1167 #define OPTION_DCT_INTERLEAVE FALSE
1168 #endif
1169 #endif
1170 #ifdef BLDOPT_REMOVE_NODE_INTERLEAVE
1171 #if BLDOPT_REMOVE_NODE_INTERLEAVE == TRUE
1172 #undef OPTION_NODE_INTERLEAVE
1173 #define OPTION_NODE_INTERLEAVE FALSE
1174 #endif
1175 #endif
1176 #ifdef BLDOPT_REMOVE_PARALLEL_TRAINING
1177 #if BLDOPT_REMOVE_PARALLEL_TRAINING == TRUE
1178 #undef OPTION_PARALLEL_TRAINING
1179 #define OPTION_PARALLEL_TRAINING FALSE
1180 #endif
1181 #endif
1182 #ifdef BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT
1183 #if BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT == TRUE
1184 #undef OPTION_ONLINE_SPARE
1185 #define OPTION_ONLINE_SPARE FALSE
1186 #endif
1187 #endif
1188 #ifdef BLDOPT_REMOVE_MEM_RESTORE_SUPPORT
1189 #if BLDOPT_REMOVE_MEM_RESTORE_SUPPORT == TRUE
1190 #undef OPTION_MEM_RESTORE
1191 #define OPTION_MEM_RESTORE FALSE
1192 #endif
1193 #endif
1194 #ifdef BLDOPT_REMOVE_HW_DQS_REC_EN_SEED_TRAINING
1195 #if BLDOPT_REMOVE_HW_DQS_REC_EN_SEED_TRAINING == TRUE
1196 #undef OPTION_HW_DQS_REC_EN_SEED_TRAINING
1197 #define OPTION_HW_DQS_REC_EN_SEED_TRAINING FALSE
1198 #endif
1199 #endif
1200 #ifdef BLDOPT_REMOVE_ACPI_PSTATES
1201 #if BLDOPT_REMOVE_ACPI_PSTATES == TRUE
1202 #undef OPTION_ACPI_PSTATES
1203 #define OPTION_ACPI_PSTATES FALSE
1204 #endif
1205 #endif
1206 #ifdef BLDOPT_REMOVE_SRAT
1207 #if BLDOPT_REMOVE_SRAT == TRUE
1208 #undef OPTION_SRAT
1209 #define OPTION_SRAT FALSE
1210 #endif
1211 #endif
1212 #ifdef BLDOPT_REMOVE_SLIT
1213 #if BLDOPT_REMOVE_SLIT == TRUE
1214 #undef OPTION_SLIT
1215 #define OPTION_SLIT FALSE
1216 #endif
1217 #endif
1218 #ifdef BLDOPT_REMOVE_WHEA
1219 #if BLDOPT_REMOVE_WHEA == TRUE
1220 #undef OPTION_WHEA
1221 #define OPTION_WHEA FALSE
1222 #endif
1223 #endif
1224 #ifdef BLDOPT_REMOVE_DMI
1225 #if BLDOPT_REMOVE_DMI == TRUE
1226 #undef OPTION_DMI
1227 #define OPTION_DMI FALSE
1228 #endif
1229 #endif
1230 #ifdef BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR
1231 #if BLDOPT_REMOVE_ADDR_TO_CS_TRANSLATOR == TRUE
1232 #undef OPTION_ADDR_TO_CS_TRANSLATOR
1233 #define OPTION_ADDR_TO_CS_TRANSLATOR FALSE
1234 #endif
1235 #endif
1237 #ifdef BLDOPT_REMOVE_HT_ASSIST
1238 #if BLDOPT_REMOVE_HT_ASSIST == TRUE
1239 #undef OPTION_HT_ASSIST
1240 #define OPTION_HT_ASSIST FALSE
1241 #endif
1242 #endif
1244 #ifdef BLDOPT_REMOVE_ATM_MODE
1245 #if BLDOPT_REMOVE_ATM_MODE == TRUE
1246 #undef OPTION_ATM_MODE
1247 #define OPTION_ATM_MODE FALSE
1248 #endif
1249 #endif
1251 #ifdef BLDOPT_REMOVE_MSG_BASED_C1E
1252 #if BLDOPT_REMOVE_MSG_BASED_C1E == TRUE
1253 #undef OPTION_MSG_BASED_C1E
1254 #define OPTION_MSG_BASED_C1E FALSE
1255 #endif
1256 #endif
1258 #ifdef BLDOPT_REMOVE_C6_STATE
1259 #if BLDOPT_REMOVE_C6_STATE == TRUE
1260 #undef OPTION_C6_STATE
1261 #define OPTION_C6_STATE FALSE
1262 #endif
1263 #endif
1265 #ifdef BLDOPT_REMOVE_GFX_RECOVERY
1266 #if BLDOPT_REMOVE_GFX_RECOVERY == TRUE
1267 #undef OPTION_GFX_RECOVERY
1268 #define OPTION_GFX_RECOVERY FALSE
1269 #endif
1270 #endif
1272 #ifdef BLDCFG_REMOVE_ACPI_PSTATES_PPC
1273 #if BLDCFG_REMOVE_ACPI_PSTATES_PPC == TRUE
1274 #undef CFG_ACPI_PSTATES_PPC
1275 #define CFG_ACPI_PSTATES_PPC FALSE
1276 #endif
1277 #endif
1279 #ifdef BLDCFG_REMOVE_ACPI_PSTATES_PCT
1280 #if BLDCFG_REMOVE_ACPI_PSTATES_PCT == TRUE
1281 #undef CFG_ACPI_PSTATES_PCT
1282 #define CFG_ACPI_PSTATES_PCT FALSE
1283 #endif
1284 #endif
1286 #ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSD
1287 #if BLDCFG_REMOVE_ACPI_PSTATES_PSD == TRUE
1288 #undef CFG_ACPI_PSTATES_PSD
1289 #define CFG_ACPI_PSTATES_PSD FALSE
1290 #endif
1291 #endif
1293 #ifdef BLDCFG_REMOVE_ACPI_PSTATES_PSS
1294 #if BLDCFG_REMOVE_ACPI_PSTATES_PSS == TRUE
1295 #undef CFG_ACPI_PSTATES_PSS
1296 #define CFG_ACPI_PSTATES_PSS FALSE
1297 #endif
1298 #endif
1300 #ifdef BLDCFG_REMOVE_ACPI_PSTATES_XPSS
1301 #if BLDCFG_REMOVE_ACPI_PSTATES_XPSS == TRUE
1302 #undef CFG_ACPI_PSTATES_XPSS
1303 #define CFG_ACPI_PSTATES_XPSS FALSE
1304 #endif
1305 #endif
1307 #ifdef BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT
1308 #if BLDOPT_REMOVE_LOW_POWER_STATE_FOR_PROCHOT == TRUE
1309 #undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT
1310 #define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT FALSE
1311 #endif
1312 #endif
1314 #ifdef BLDCFG_PSTATE_HPC_MODE
1315 #if BLDCFG_PSTATE_HPC_MODE == TRUE
1316 #undef OPTION_CPU_PSTATE_HPC_MODE
1317 #define OPTION_CPU_PSTATE_HPC_MODE TRUE
1318 #endif
1319 #endif
1321 #ifdef BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT
1322 #if BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT == TRUE
1323 #undef CFG_ACPI_PSTATE_PSD_INDPX
1324 #define CFG_ACPI_PSTATE_PSD_INDPX TRUE
1325 #endif
1326 #endif
1328 #ifdef BLDCFG_VRM_HIGH_SPEED_ENABLE
1329 #if BLDCFG_VRM_HIGH_SPEED_ENABLE == TRUE
1330 #undef CFG_VRM_HIGH_SPEED_ENABLE
1331 #define CFG_VRM_HIGH_SPEED_ENABLE TRUE
1332 #endif
1333 #endif
1335 #ifdef BLDCFG_VRM_NB_HIGH_SPEED_ENABLE
1336 #if BLDCFG_VRM_NB_HIGH_SPEED_ENABLE == TRUE
1337 #undef CFG_VRM_NB_HIGH_SPEED_ENABLE
1338 #define CFG_VRM_NB_HIGH_SPEED_ENABLE TRUE
1339 #endif
1340 #endif
1342 #ifdef BLDCFG_STARTING_BUSNUM
1343 #define CFG_STARTING_BUSNUM (BLDCFG_STARTING_BUSNUM)
1344 #else
1345 #define CFG_STARTING_BUSNUM (0)
1346 #endif
1348 #ifdef BLDCFG_AMD_PLATFORM_TYPE
1349 #define CFG_AMD_PLATFORM_TYPE BLDCFG_AMD_PLATFORM_TYPE
1350 #else
1351 #define CFG_AMD_PLATFORM_TYPE 0
1352 #endif
1356 #ifdef BLDCFG_MAXIMUM_BUSNUM
1357 #define CFG_MAXIMUM_BUSNUM (BLDCFG_MAXIMUM_BUSNUM)
1358 #else
1359 #define CFG_MAXIMUM_BUSNUM (0xF8)
1360 #endif
1362 #ifdef BLDCFG_ALLOCATED_BUSNUM
1363 #define CFG_ALLOCATED_BUSNUM (BLDCFG_ALLOCATED_BUSNUM)
1364 #else
1365 #define CFG_ALLOCATED_BUSNUM (0x20)
1366 #endif
1368 #ifdef BLDCFG_BUID_SWAP_LIST
1369 #define CFG_BUID_SWAP_LIST (BLDCFG_BUID_SWAP_LIST)
1370 #else
1371 #define CFG_BUID_SWAP_LIST (NULL)
1372 #endif
1374 #ifdef BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST
1375 #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST (BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST)
1376 #else
1377 #define CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST (NULL)
1378 #endif
1380 #ifdef BLDCFG_HTFABRIC_LIMITS_LIST
1381 #define CFG_HTFABRIC_LIMITS_LIST (BLDCFG_HTFABRIC_LIMITS_LIST)
1382 #else
1383 #define CFG_HTFABRIC_LIMITS_LIST (NULL)
1384 #endif
1386 #ifdef BLDCFG_HTCHAIN_LIMITS_LIST
1387 #define CFG_HTCHAIN_LIMITS_LIST (BLDCFG_HTCHAIN_LIMITS_LIST)
1388 #else
1389 #define CFG_HTCHAIN_LIMITS_LIST (NULL)
1390 #endif
1392 #ifdef BLDCFG_BUS_NUMBERS_LIST
1393 #define CFG_BUS_NUMBERS_LIST (BLDCFG_BUS_NUMBERS_LIST)
1394 #else
1395 #define CFG_BUS_NUMBERS_LIST (NULL)
1396 #endif
1398 #ifdef BLDCFG_IGNORE_LINK_LIST
1399 #define CFG_IGNORE_LINK_LIST (BLDCFG_IGNORE_LINK_LIST)
1400 #else
1401 #define CFG_IGNORE_LINK_LIST (NULL)
1402 #endif
1404 #ifdef BLDCFG_LINK_SKIP_REGANG_LIST
1405 #define CFG_LINK_SKIP_REGANG_LIST (BLDCFG_LINK_SKIP_REGANG_LIST)
1406 #else
1407 #define CFG_LINK_SKIP_REGANG_LIST (NULL)
1408 #endif
1410 #ifdef BLDCFG_SET_HTCRC_SYNC_FLOOD
1411 #define CFG_SET_HTCRC_SYNC_FLOOD (BLDCFG_SET_HTCRC_SYNC_FLOOD)
1412 #else
1413 #define CFG_SET_HTCRC_SYNC_FLOOD (FALSE)
1414 #endif
1416 #ifdef BLDCFG_USE_UNIT_ID_CLUMPING
1417 #define CFG_USE_UNIT_ID_CLUMPING (BLDCFG_USE_UNIT_ID_CLUMPING)
1418 #else
1419 #define CFG_USE_UNIT_ID_CLUMPING (FALSE)
1420 #endif
1422 #ifdef BLDCFG_ADDITIONAL_TOPOLOGIES_LIST
1423 #define CFG_ADDITIONAL_TOPOLOGIES_LIST (BLDCFG_ADDITIONAL_TOPOLOGIES_LIST)
1424 #else
1425 #define CFG_ADDITIONAL_TOPOLOGIES_LIST (NULL)
1426 #endif
1428 #ifdef BLDCFG_USE_HT_ASSIST
1429 #define CFG_USE_HT_ASSIST (BLDCFG_USE_HT_ASSIST)
1430 #else
1431 #define CFG_USE_HT_ASSIST (TRUE)
1432 #endif
1434 #ifdef BLDCFG_USE_ATM_MODE
1435 #define CFG_USE_ATM_MODE (BLDCFG_USE_ATM_MODE)
1436 #else
1437 #define CFG_USE_ATM_MODE (TRUE)
1438 #endif
1440 #ifdef BLDCFG_PLATFORM_CONTROL_FLOW_MODE
1441 #define CFG_PLATFORM_CONTROL_FLOW_MODE (BLDCFG_PLATFORM_CONTROL_FLOW_MODE)
1442 #else
1443 #define CFG_PLATFORM_CONTROL_FLOW_MODE (Nfcm)
1444 #endif
1446 #ifdef BLDCFG_PERFORMANCE_HARDWARE_PREFETCHER
1447 #define CFG_PERFORMANCE_HARDWARE_PREFETCHER (BLDCFG_PERFORMANCE_HARDWARE_PREFETCHER)
1448 #else
1449 #define CFG_PERFORMANCE_HARDWARE_PREFETCHER (HARDWARE_PREFETCHER_AUTO)
1450 #endif
1452 #ifdef BLDCFG_PERFORMANCE_SOFTWARE_PREFETCHES
1453 #define CFG_PERFORMANCE_SOFTWARE_PREFETCHES (BLDCFG_PERFORMANCE_SOFTWARE_PREFETCHES)
1454 #else
1455 #define CFG_PERFORMANCE_SOFTWARE_PREFETCHES (SOFTWARE_PREFETCHES_AUTO)
1456 #endif
1458 #ifdef BLDCFG_PERFORMANCE_DRAM_PREFETCHER
1459 #define CFG_PERFORMANCE_DRAM_PREFETCHER (BLDCFG_PERFORMANCE_DRAM_PREFETCHER)
1460 #else
1461 #define CFG_PERFORMANCE_DRAM_PREFETCHER (DRAM_PREFETCHER_AUTO)
1462 #endif
1464 #ifdef BLDCFG_PLATFORM_DEEMPHASIS_LIST
1465 #define CFG_PLATFORM_DEEMPHASIS_LIST (BLDCFG_PLATFORM_DEEMPHASIS_LIST)
1466 #else
1467 #define CFG_PLATFORM_DEEMPHASIS_LIST (NULL)
1468 #endif
1470 #ifdef BLDCFG_VRM_ADDITIONAL_DELAY
1471 #define CFG_VRM_ADDITIONAL_DELAY (BLDCFG_VRM_ADDITIONAL_DELAY)
1472 #else
1473 #define CFG_VRM_ADDITIONAL_DELAY (0)
1474 #endif
1476 #ifdef BLDCFG_VRM_CURRENT_LIMIT
1477 #define CFG_VRM_CURRENT_LIMIT BLDCFG_VRM_CURRENT_LIMIT
1478 #else
1479 #define CFG_VRM_CURRENT_LIMIT 0
1480 #endif
1482 #ifdef BLDCFG_VRM_LOW_POWER_THRESHOLD
1483 #define CFG_VRM_LOW_POWER_THRESHOLD BLDCFG_VRM_LOW_POWER_THRESHOLD
1484 #else
1485 #define CFG_VRM_LOW_POWER_THRESHOLD 0
1486 #endif
1488 #ifdef BLDCFG_VRM_SLEW_RATE
1489 #define CFG_VRM_SLEW_RATE BLDCFG_VRM_SLEW_RATE
1490 #else
1491 #define CFG_VRM_SLEW_RATE DFLT_VRM_SLEW_RATE
1492 #endif
1494 #ifdef BLDCFG_VRM_INRUSH_CURRENT_LIMIT
1495 #define CFG_VRM_INRUSH_CURRENT_LIMIT BLDCFG_VRM_INRUSH_CURRENT_LIMIT
1496 #else
1497 #define CFG_VRM_INRUSH_CURRENT_LIMIT 0
1498 #endif
1500 #ifdef BLDCFG_VRM_NB_ADDITIONAL_DELAY
1501 #define CFG_VRM_NB_ADDITIONAL_DELAY (BLDCFG_VRM_NB_ADDITIONAL_DELAY)
1502 #else
1503 #define CFG_VRM_NB_ADDITIONAL_DELAY (0)
1504 #endif
1506 #ifdef BLDCFG_VRM_NB_CURRENT_LIMIT
1507 #define CFG_VRM_NB_CURRENT_LIMIT BLDCFG_VRM_NB_CURRENT_LIMIT
1508 #else
1509 #define CFG_VRM_NB_CURRENT_LIMIT (0)
1510 #endif
1512 #ifdef BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
1513 #define CFG_VRM_NB_LOW_POWER_THRESHOLD BLDCFG_VRM_NB_LOW_POWER_THRESHOLD
1514 #else
1515 #define CFG_VRM_NB_LOW_POWER_THRESHOLD (0)
1516 #endif
1518 #ifdef BLDCFG_VRM_NB_SLEW_RATE
1519 #define CFG_VRM_NB_SLEW_RATE BLDCFG_VRM_NB_SLEW_RATE
1520 #else
1521 #define CFG_VRM_NB_SLEW_RATE DFLT_VRM_SLEW_RATE
1522 #endif
1524 #ifdef BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT
1525 #define CFG_VRM_NB_INRUSH_CURRENT_LIMIT BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT
1526 #else
1527 #define CFG_VRM_NB_INRUSH_CURRENT_LIMIT (0)
1528 #endif
1531 #ifdef BLDCFG_PLAT_NUM_IO_APICS
1532 #define CFG_PLAT_NUM_IO_APICS BLDCFG_PLAT_NUM_IO_APICS
1533 #else
1534 #define CFG_PLAT_NUM_IO_APICS 0
1535 #endif
1537 #ifdef BLDCFG_MEM_INIT_PSTATE
1538 #define CFG_MEM_INIT_PSTATE BLDCFG_MEM_INIT_PSTATE
1539 #else
1540 #define CFG_MEM_INIT_PSTATE 0
1541 #endif
1543 #ifdef BLDCFG_PLATFORM_C1E_MODE
1544 #define CFG_C1E_MODE BLDCFG_PLATFORM_C1E_MODE
1545 #else
1546 #define CFG_C1E_MODE C1eModeDisabled
1547 #endif
1549 #ifdef BLDCFG_PLATFORM_C1E_OPDATA
1550 #define CFG_C1E_OPDATA BLDCFG_PLATFORM_C1E_OPDATA
1551 #else
1552 #define CFG_C1E_OPDATA 0
1553 #endif
1555 #ifdef BLDCFG_PLATFORM_C1E_OPDATA1
1556 #define CFG_C1E_OPDATA1 BLDCFG_PLATFORM_C1E_OPDATA1
1557 #else
1558 #define CFG_C1E_OPDATA1 0
1559 #endif
1561 #ifdef BLDCFG_PLATFORM_C1E_OPDATA2
1562 #define CFG_C1E_OPDATA2 BLDCFG_PLATFORM_C1E_OPDATA2
1563 #else
1564 #define CFG_C1E_OPDATA2 0
1565 #endif
1567 #ifdef BLDCFG_PLATFORM_C1E_OPDATA3
1568 #define CFG_C1E_OPDATA3 BLDCFG_PLATFORM_C1E_OPDATA3
1569 #else
1570 #define CFG_C1E_OPDATA3 0
1571 #endif
1573 #ifdef BLDCFG_PLATFORM_CSTATE_MODE
1574 #define CFG_CSTATE_MODE BLDCFG_PLATFORM_CSTATE_MODE
1575 #else
1576 #define CFG_CSTATE_MODE CStateModeDisabled
1577 #endif
1579 #ifdef BLDCFG_PLATFORM_CSTATE_OPDATA
1580 #define CFG_CSTATE_OPDATA BLDCFG_PLATFORM_CSTATE_OPDATA
1581 #else
1582 #define CFG_CSTATE_OPDATA 0
1583 #endif
1585 #ifdef BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
1586 #define CFG_CSTATE_IO_BASE_ADDRESS BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS
1587 #else
1588 #define CFG_CSTATE_IO_BASE_ADDRESS 0
1589 #endif
1591 #ifdef BLDCFG_PLATFORM_CPB_MODE
1592 #define CFG_CPB_MODE BLDCFG_PLATFORM_CPB_MODE
1593 #else
1594 #define CFG_CPB_MODE CpbModeAuto
1595 #endif
1597 #ifdef BLDCFG_CORE_LEVELING_MODE
1598 #define CFG_CORE_LEVELING_MODE BLDCFG_CORE_LEVELING_MODE
1599 #else
1600 #define CFG_CORE_LEVELING_MODE 0
1601 #endif
1603 #ifdef BLDCFG_AMD_PSTATE_CAP_VALUE
1604 #define CFG_AMD_PSTATE_CAP_VALUE BLDCFG_AMD_PSTATE_CAP_VALUE
1605 #else
1606 #define CFG_AMD_PSTATE_CAP_VALUE 0
1607 #endif
1609 #ifdef BLDCFG_HEAP_DRAM_ADDRESS
1610 #define CFG_HEAP_DRAM_ADDRESS BLDCFG_HEAP_DRAM_ADDRESS
1611 #else
1612 #define CFG_HEAP_DRAM_ADDRESS AMD_HEAP_RAM_ADDRESS
1613 #endif
1615 #ifdef BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
1616 #define CFG_MEMORY_BUS_FREQUENCY_LIMIT BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT
1617 #else
1618 #define CFG_MEMORY_BUS_FREQUENCY_LIMIT DDR800_FREQUENCY
1619 #endif
1621 #ifdef BLDCFG_MEMORY_MODE_UNGANGED
1622 #define CFG_MEMORY_MODE_UNGANGED BLDCFG_MEMORY_MODE_UNGANGED
1623 #else
1624 #define CFG_MEMORY_MODE_UNGANGED TRUE
1625 #endif
1627 #ifdef BLDCFG_MEMORY_QUAD_RANK_CAPABLE
1628 #define CFG_MEMORY_QUAD_RANK_CAPABLE BLDCFG_MEMORY_QUAD_RANK_CAPABLE
1629 #else
1630 #define CFG_MEMORY_QUAD_RANK_CAPABLE TRUE
1631 #endif
1633 #ifdef BLDCFG_MEMORY_QUADRANK_TYPE
1634 #define CFG_MEMORY_QUADRANK_TYPE BLDCFG_MEMORY_QUADRANK_TYPE
1635 #else
1636 #define CFG_MEMORY_QUADRANK_TYPE DFLT_MEMORY_QUADRANK_TYPE
1637 #endif
1639 #ifdef BLDCFG_MEMORY_RDIMM_CAPABLE
1640 #define CFG_MEMORY_RDIMM_CAPABLE BLDCFG_MEMORY_RDIMM_CAPABLE
1641 #else
1642 #define CFG_MEMORY_RDIMM_CAPABLE TRUE
1643 #endif
1645 #ifdef BLDCFG_MEMORY_LRDIMM_CAPABLE
1646 #define CFG_MEMORY_LRDIMM_CAPABLE BLDCFG_MEMORY_LRDIMM_CAPABLE
1647 #else
1648 #define CFG_MEMORY_LRDIMM_CAPABLE TRUE
1649 #endif
1651 #ifdef BLDCFG_MEMORY_UDIMM_CAPABLE
1652 #define CFG_MEMORY_UDIMM_CAPABLE BLDCFG_MEMORY_UDIMM_CAPABLE
1653 #else
1654 #define CFG_MEMORY_UDIMM_CAPABLE TRUE
1655 #endif
1657 #ifdef BLDCFG_MEMORY_SODIMM_CAPABLE
1658 #define CFG_MEMORY_SODIMM_CAPABLE BLDCFG_MEMORY_SODIMM_CAPABLE
1659 #else
1660 #define CFG_MEMORY_SODIMM_CAPABLE FALSE
1661 #endif
1663 #ifdef BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB
1664 #define CFG_LIMIT_MEMORY_TO_BELOW_1TB BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB
1665 #else
1666 #define CFG_LIMIT_MEMORY_TO_BELOW_1TB TRUE
1667 #endif
1669 #ifdef BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
1670 #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING
1671 #else
1672 #define CFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE
1673 #endif
1675 #ifdef BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
1676 #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING
1677 #else
1678 #define CFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
1679 #endif
1681 #ifdef BLDCFG_MEMORY_CHANNEL_INTERLEAVING
1682 #define CFG_MEMORY_CHANNEL_INTERLEAVING BLDCFG_MEMORY_CHANNEL_INTERLEAVING
1683 #else
1684 #define CFG_MEMORY_CHANNEL_INTERLEAVING TRUE
1685 #endif
1687 #ifdef BLDCFG_MEMORY_POWER_DOWN
1688 #define CFG_MEMORY_POWER_DOWN BLDCFG_MEMORY_POWER_DOWN
1689 #else
1690 #define CFG_MEMORY_POWER_DOWN FALSE
1691 #endif
1693 #ifdef BLDCFG_POWER_DOWN_MODE
1694 #define CFG_POWER_DOWN_MODE BLDCFG_POWER_DOWN_MODE
1695 #else
1696 #define CFG_POWER_DOWN_MODE POWER_DOWN_MODE_AUTO
1697 #endif
1699 #ifdef BLDCFG_ONLINE_SPARE
1700 #define CFG_ONLINE_SPARE BLDCFG_ONLINE_SPARE
1701 #else
1702 #define CFG_ONLINE_SPARE FALSE
1703 #endif
1705 #ifdef BLDCFG_MEMORY_PARITY_ENABLE
1706 #define CFG_MEMORY_PARITY_ENABLE BLDCFG_MEMORY_PARITY_ENABLE
1707 #else
1708 #define CFG_MEMORY_PARITY_ENABLE FALSE
1709 #endif
1711 #ifdef BLDCFG_BANK_SWIZZLE
1712 #define CFG_BANK_SWIZZLE BLDCFG_BANK_SWIZZLE
1713 #else
1714 #define CFG_BANK_SWIZZLE TRUE
1715 #endif
1717 #ifdef BLDCFG_TIMING_MODE_SELECT
1718 #define CFG_TIMING_MODE_SELECT BLDCFG_TIMING_MODE_SELECT
1719 #else
1720 #define CFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
1721 #endif
1723 #ifdef BLDCFG_MEMORY_CLOCK_SELECT
1724 #define CFG_MEMORY_CLOCK_SELECT BLDCFG_MEMORY_CLOCK_SELECT
1725 #else
1726 #define CFG_MEMORY_CLOCK_SELECT DDR800_FREQUENCY
1727 #endif
1729 #ifdef BLDCFG_DQS_TRAINING_CONTROL
1730 #define CFG_DQS_TRAINING_CONTROL BLDCFG_DQS_TRAINING_CONTROL
1731 #else
1732 #define CFG_DQS_TRAINING_CONTROL TRUE
1733 #endif
1735 #ifdef BLDCFG_IGNORE_SPD_CHECKSUM
1736 #define CFG_IGNORE_SPD_CHECKSUM BLDCFG_IGNORE_SPD_CHECKSUM
1737 #else
1738 #define CFG_IGNORE_SPD_CHECKSUM FALSE
1739 #endif
1741 #ifdef BLDCFG_USE_BURST_MODE
1742 #define CFG_USE_BURST_MODE BLDCFG_USE_BURST_MODE
1743 #else
1744 #define CFG_USE_BURST_MODE FALSE
1745 #endif
1747 #ifdef BLDCFG_MEMORY_ALL_CLOCKS_ON
1748 #define CFG_MEMORY_ALL_CLOCKS_ON BLDCFG_MEMORY_ALL_CLOCKS_ON
1749 #else
1750 #define CFG_MEMORY_ALL_CLOCKS_ON FALSE
1751 #endif
1753 #ifdef BLDCFG_ENABLE_ECC_FEATURE
1754 #define CFG_ENABLE_ECC_FEATURE BLDCFG_ENABLE_ECC_FEATURE
1755 #else
1756 #define CFG_ENABLE_ECC_FEATURE TRUE
1757 #endif
1759 #ifdef BLDCFG_ECC_REDIRECTION
1760 #define CFG_ECC_REDIRECTION BLDCFG_ECC_REDIRECTION
1761 #else
1762 #define CFG_ECC_REDIRECTION FALSE
1763 #endif
1765 #ifdef BLDCFG_SCRUB_DRAM_RATE
1766 #define CFG_SCRUB_DRAM_RATE BLDCFG_SCRUB_DRAM_RATE
1767 #else
1768 #define CFG_SCRUB_DRAM_RATE DFLT_SCRUB_DRAM_RATE
1769 #endif
1771 #ifdef BLDCFG_SCRUB_L2_RATE
1772 #define CFG_SCRUB_L2_RATE BLDCFG_SCRUB_L2_RATE
1773 #else
1774 #define CFG_SCRUB_L2_RATE DFLT_SCRUB_L2_RATE
1775 #endif
1777 #ifdef BLDCFG_SCRUB_L3_RATE
1778 #define CFG_SCRUB_L3_RATE BLDCFG_SCRUB_L3_RATE
1779 #else
1780 #define CFG_SCRUB_L3_RATE DFLT_SCRUB_L3_RATE
1781 #endif
1783 #ifdef BLDCFG_SCRUB_IC_RATE
1784 #define CFG_SCRUB_IC_RATE BLDCFG_SCRUB_IC_RATE
1785 #else
1786 #define CFG_SCRUB_IC_RATE DFLT_SCRUB_IC_RATE
1787 #endif
1789 #ifdef BLDCFG_SCRUB_DC_RATE
1790 #define CFG_SCRUB_DC_RATE BLDCFG_SCRUB_DC_RATE
1791 #else
1792 #define CFG_SCRUB_DC_RATE DFLT_SCRUB_DC_RATE
1793 #endif
1795 #ifdef BLDCFG_ECC_SYNC_FLOOD
1796 #define CFG_ECC_SYNC_FLOOD BLDCFG_ECC_SYNC_FLOOD
1797 #else
1798 #define CFG_ECC_SYNC_FLOOD TRUE
1799 #endif
1801 #ifdef BLDCFG_ECC_SYMBOL_SIZE
1802 #define CFG_ECC_SYMBOL_SIZE BLDCFG_ECC_SYMBOL_SIZE
1803 #else
1804 #define CFG_ECC_SYMBOL_SIZE 0
1805 #endif
1807 #ifdef BLDCFG_1GB_ALIGN
1808 #define CFG_1GB_ALIGN BLDCFG_1GB_ALIGN
1809 #else
1810 #define CFG_1GB_ALIGN FALSE
1811 #endif
1813 #ifdef BLDCFG_UMA_ALLOCATION_MODE
1814 #define CFG_UMA_MODE BLDCFG_UMA_ALLOCATION_MODE
1815 #else
1816 #define CFG_UMA_MODE UMA_AUTO
1817 #endif
1819 #ifdef BLDCFG_FORCE_TRAINING_MODE
1820 #define CFG_FORCE_TRAIN_MODE BLDCFG_FORCE_TRAINING_MODE
1821 #else
1822 #define CFG_FORCE_TRAIN_MODE FORCE_TRAIN_AUTO
1823 #endif
1825 #ifdef BLDCFG_UMA_ALLOCATION_SIZE
1826 #define CFG_UMA_SIZE BLDCFG_UMA_ALLOCATION_SIZE
1827 #else
1828 #define CFG_UMA_SIZE 0
1829 #endif
1831 #ifdef BLDCFG_UMA_ABOVE4G_SUPPORT
1832 #define CFG_UMA_ABOVE4G BLDCFG_UMA_ABOVE4G_SUPPORT
1833 #else
1834 #define CFG_UMA_ABOVE4G FALSE
1835 #endif
1837 #ifdef BLDCFG_UMA_ALIGNMENT
1838 #define CFG_UMA_ALIGNMENT BLDCFG_UMA_ALIGNMENT
1839 #else
1840 #define CFG_UMA_ALIGNMENT NO_UMA_ALIGNED
1841 #endif
1843 #ifdef BLDCFG_PROCESSOR_SCOPE_IN_SB
1844 #define CFG_PROCESSOR_SCOPE_IN_SB BLDCFG_PROCESSOR_SCOPE_IN_SB
1845 #else
1846 #define CFG_PROCESSOR_SCOPE_IN_SB FALSE
1847 #endif
1849 #ifdef BLDCFG_S3_LATE_RESTORE
1850 #define CFG_S3_LATE_RESTORE BLDCFG_S3_LATE_RESTORE
1851 #else
1852 #define CFG_S3_LATE_RESTORE TRUE
1853 #endif
1855 #ifdef BLDCFG_USE_32_BYTE_REFRESH
1856 #define CFG_USE_32_BYTE_REFRESH (BLDCFG_USE_32_BYTE_REFRESH)
1857 #else
1858 #define CFG_USE_32_BYTE_REFRESH (FALSE)
1859 #endif
1861 #ifdef BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY
1862 #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY)
1863 #else
1864 #define CFG_USE_VARIABLE_MCT_ISOC_PRIORITY (FALSE)
1865 #endif
1867 #ifdef BLDCFG_PROCESSOR_SCOPE_NAME0
1868 #define CFG_PROCESSOR_SCOPE_NAME0 BLDCFG_PROCESSOR_SCOPE_NAME0
1869 #else
1870 #define CFG_PROCESSOR_SCOPE_NAME0 SCOPE_NAME_VALUE
1871 #endif
1873 #ifdef BLDCFG_PROCESSOR_SCOPE_NAME1
1874 #define CFG_PROCESSOR_SCOPE_NAME1 BLDCFG_PROCESSOR_SCOPE_NAME1
1875 #else
1876 #define CFG_PROCESSOR_SCOPE_NAME1 SCOPE_NAME_VALUE1
1877 #endif
1879 #ifdef BLDCFG_CFG_GNB_HD_AUDIO
1880 #define CFG_GNB_HD_AUDIO BLDCFG_CFG_GNB_HD_AUDIO
1881 #else
1882 #define CFG_GNB_HD_AUDIO TRUE
1883 #endif
1885 #ifdef BLDCFG_CFG_ABM_SUPPORT
1886 #define CFG_ABM_SUPPORT BLDCFG_CFG_ABM_SUPPORT
1887 #else
1888 #define CFG_ABM_SUPPORT FALSE
1889 #endif
1891 #ifdef BLDCFG_CFG_DYNAMIC_REFRESH_RATE
1892 #define CFG_DINAMIC_REFRESH_RATE BLDCFG_CFG_DYNAMIC_REFRESH_RATE
1893 #else
1894 #define CFG_DYNAMIC_REFRESH_RATE 0
1895 #endif
1897 #ifdef BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
1898 #define CFG_LCD_BACK_LIGHT_CONTROL BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
1899 #else
1900 #define CFG_LCD_BACK_LIGHT_CONTROL 0
1901 #endif
1903 #ifdef BLDCFG_STEREO_3D_PINOUT
1904 #define CFG_GNB_STEREO_3D_PINOUT BLDCFG_STEREO_3D_PINOUT
1905 #else
1906 #define CFG_GNB_STEREO_3D_PINOUT 0
1907 #endif
1909 #ifdef BLDCFG_REMOTE_DISPLAY_SUPPORT
1910 #define CFG_GNB_REMOTE_DISPLAY_SUPPORT BLDCFG_REMOTE_DISPLAY_SUPPORT
1911 #else
1912 #define CFG_GNB_REMOTE_DISPLAY_SUPPORT FALSE
1913 #endif
1915 #ifdef BLDCFG_IGPU_SUBSYSTEM_ID
1916 #define CFG_GNB_IGPU_SSID BLDCFG_IGPU_SUBSYSTEM_ID
1917 #else
1918 #define CFG_GNB_IGPU_SSID 0
1919 #endif
1921 #ifdef BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID
1922 #define CFG_GNB_HDAUDIO_SSID BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID
1923 #else
1924 #define CFG_GNB_HDAUDIO_SSID 0
1925 #endif
1927 #ifdef BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID
1928 #define CFG_GNB_PCIE_SSID BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID
1929 #else
1930 #define CFG_GNB_PCIE_SSID 0x12341022
1931 #endif
1933 #ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM
1934 #define CFG_GFX_LVDS_SPREAD_SPECTRUM BLDCFG_GFX_LVDS_SPREAD_SPECTRUM
1935 #else
1936 #define CFG_GFX_LVDS_SPREAD_SPECTRUM 0
1937 #endif
1939 #ifdef BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE
1940 #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE
1941 #else
1942 #define CFG_GFX_LVDS_SPREAD_SPECTRUM_RATE 0
1943 #endif
1945 #ifdef BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
1946 #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM
1947 #else
1948 #define CFG_PCIE_REFCLK_SPREAD_SPECTRUM 0
1949 #endif
1951 #ifdef BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
1952 #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS BLDCFG_CFG_TEMP_PCIE_MMIO_BASE_ADDRESS
1953 #else
1954 #define CFG_TEMP_PCIE_MMIO_BASE_ADDRESS 0xD0000000
1955 #endif
1957 #ifdef BLDCFG_ENABLE_EXTERNAL_VREF_FEATURE
1958 #define CFG_ENABLE_EXTERNAL_VREF BLDCFG_ENABLE_EXTERNAL_VREF_FEATURE
1959 #else
1960 #define CFG_ENABLE_EXTERNAL_VREF FALSE
1961 #endif
1963 #ifdef BLDOPT_REMOVE_EARLY_SAMPLES
1964 #if BLDOPT_REMOVE_EARLY_SAMPLES == TRUE
1965 #undef OPTION_EARLY_SAMPLES
1966 #define OPTION_EARLY_SAMPLES FALSE
1967 #else
1968 #undef OPTION_EARLY_SAMPLES
1969 #define OPTION_EARLY_SAMPLES TRUE
1970 #endif
1971 #endif
1973 #ifdef BLDOPT_REMOVE_ALIB
1974 #if BLDOPT_REMOVE_ALIB == TRUE
1975 #undef OPTION_ALIB
1976 #define OPTION_ALIB FALSE
1977 #else
1978 #undef OPTION_ALIB
1979 #define OPTION_ALIB TRUE
1980 #endif
1981 #endif
1983 #ifdef BLDOPT_REMOVE_FCH_COMPONENT
1984 #if BLDOPT_REMOVE_FCH_COMPONENT == TRUE
1985 #undef FCH_SUPPORT
1986 #define FCH_SUPPORT FALSE
1987 #endif
1988 #endif
1990 #ifdef BLDCFG_IOMMU_SUPPORT
1991 #define CFG_IOMMU_SUPPORT BLDCFG_IOMMU_SUPPORT
1992 #else
1993 #define CFG_IOMMU_SUPPORT TRUE
1994 #endif
1996 #ifdef BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE
1997 #define CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE
1998 #else
1999 #define CFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE 0
2000 #endif
2002 #ifdef BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL
2003 #define CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL
2004 #else
2005 #define CFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL 0
2006 #endif
2008 #ifdef BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON
2009 #define CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON
2010 #else
2011 #define CFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON 0
2012 #endif
2014 #ifdef BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE
2015 #define CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE
2016 #else
2017 #define CFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE 0
2018 #endif
2020 #ifdef BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY
2021 #define CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY
2022 #else
2023 #define CFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY 0
2024 #endif
2026 #ifdef BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON
2027 #define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON
2028 #else
2029 #define CFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 0
2030 #endif
2032 #ifdef BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL
2033 #define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL
2034 #else
2035 #define CFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 0
2036 #endif
2038 #ifdef BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ
2039 #define CFG_LVDS_MAX_PIXEL_CLOCK_FREQ BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ
2040 #else
2041 #define CFG_LVDS_MAX_PIXEL_CLOCK_FREQ 0
2042 #endif
2044 #ifdef BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE
2045 #define CFG_LCD_BIT_DEPTH_CONTROL_VALUE BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE
2046 #else
2047 #define CFG_LCD_BIT_DEPTH_CONTROL_VALUE 0
2048 #endif
2051 // BLDCFG_LVDS_24BBP_PANEL_MODE
2052 // This specifies the LVDS 24 BBP mode.
2053 // 0 - Use LDI mode (default).
2054 // 1 - Use FPDI mode.
2055 #ifdef BLDCFG_LVDS_24BBP_PANEL_MODE
2056 #define CFG_LVDS_24BBP_PANEL_MODE BLDCFG_LVDS_24BBP_PANEL_MODE
2057 #else
2058 #define CFG_LVDS_24BBP_PANEL_MODE 0
2059 #endif
2061 #ifdef BLDCFG_LVDS_MISC_888_FPDI_MODE
2062 #define CFG_LVDS_MISC_888_FPDI_MODE BLDCFG_LVDS_MISC_888_FPDI_MODE
2063 #else
2064 #define CFG_LVDS_MISC_888_FPDI_MODE FALSE
2065 #endif
2067 #ifdef BLDCFG_LVDS_MISC_DL_CH_SWAP
2068 #define CFG_LVDS_MISC_DL_CH_SWAP BLDCFG_LVDS_MISC_DL_CH_SWAP
2069 #else
2070 #define CFG_LVDS_MISC_DL_CH_SWAP FALSE
2071 #endif
2073 #ifdef BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW
2074 #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW
2075 #else
2076 #define CFG_LVDS_MISC_VSYNC_ACTIVE_LOW FALSE
2077 #endif
2079 #ifdef BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW
2080 #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW
2081 #else
2082 #define CFG_LVDS_MISC_HSYNC_ACTIVE_LOW FALSE
2083 #endif
2085 #ifdef BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW
2086 #define CFG_LVDS_MISC_BLON_ACTIVE_LOW BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW
2087 #else
2088 #define CFG_LVDS_MISC_BLON_ACTIVE_LOW FALSE
2089 #endif
2091 #ifdef BLDCFG_FORCE_MICROSERVER
2092 #define CFG_FORCE_MICROSERVER BLDCFG_FORCE_MICROSERVER
2093 #else
2094 #define CFG_FORCE_MICROSERVER FALSE
2095 #endif
2097 #ifdef BLDCFG_PLATFORM_POWER_POLICY_MODE
2098 #define CFG_PLATFORM_POWER_POLICY_MODE (BLDCFG_PLATFORM_POWER_POLICY_MODE)
2099 #else
2100 #define CFG_PLATFORM_POWER_POLICY_MODE (Performance)
2101 #endif
2103 #ifdef BLDCFG_PCI_MMIO_BASE
2104 #define CFG_PCI_MMIO_BASE (BLDCFG_PCI_MMIO_BASE)
2105 #else
2106 #define CFG_PCI_MMIO_BASE (0)
2107 #endif
2109 #ifdef BLDCFG_PCI_MMIO_SIZE
2110 #define CFG_PCI_MMIO_SIZE (BLDCFG_PCI_MMIO_SIZE)
2111 #else
2112 #define CFG_PCI_MMIO_SIZE (0)
2113 #endif
2115 #ifdef BLDCFG_AP_MTRR_SETTINGS_LIST
2116 #define CFG_AP_MTRR_SETTINGS_LIST (BLDCFG_AP_MTRR_SETTINGS_LIST)
2117 #else
2118 #define CFG_AP_MTRR_SETTINGS_LIST (NULL)
2119 #endif
2121 #ifdef BLDCFG_IOMMU_EXCLUSION_RANGE_LIST
2122 #define CFG_IOMMU_EXCLUSION_RANGE_LIST (BLDCFG_IOMMU_EXCLUSION_RANGE_LIST)
2123 #else
2124 #define CFG_IOMMU_EXCLUSION_RANGE_LIST (NULL)
2125 #endif
2127 /*---------------------------------------------------------------------------
2128 * Processing the options: Third, perform the option cross checks
2129 *--------------------------------------------------------------------------*/
2130 // Assure that at least one type of memory support is included
2131 #if OPTION_UDIMMS == FALSE
2132 #if OPTION_RDIMMS == FALSE
2133 #if OPTION_SODIMMS == FALSE
2134 #if OPTION_LRDIMMS == FALSE
2135 #error BLDOPT: No DIMM support selected. Either BLDOPT_REMOVE_UDIMMS_SUPPORT or BLDOPT_REMOVE_RDIMMS_SUPPORT or BLDOPT_REMOVE_SODIMMS_SUPPORT or BLDOPT_REMOVE_LRDIMMS_SUPPORT must be FALSE.
2136 #endif
2137 #endif
2138 #endif
2139 #endif
2140 // Ensure at least one dimm type is capable
2141 #if CFG_MEMORY_RDIMM_CAPABLE == FALSE
2142 #if CFG_MEMORY_UDIMM_CAPABLE == FALSE
2143 #if CFG_MEMORY_SODIMM_CAPABLE == FALSE
2144 #if CFG_MEMORY_LRDIMM_CAPABLE == FALSE
2145 #error BLDCFG: No dimm type is capable
2146 #endif
2147 #endif
2148 #endif
2149 #endif
2150 // Check LRDIMM CODE and LRDIMM CFG item
2151 #if CFG_MEMORY_LRDIMM_CAPABLE == FALSE
2152 #if BLDOPT_REMOVE_LRDIMMS_SUPPORT == TRUE
2153 #error Warning: LRDIMM capability is false, but LRIDMM support code included
2154 #endif
2155 #endif
2156 // Turn off multi-socket based features if only one node...
2157 #if OPTION_MULTISOCKET == FALSE
2158 #undef OPTION_PARALLEL_TRAINING
2159 #define OPTION_PARALLEL_TRAINING FALSE
2160 #undef OPTION_NODE_INTERLEAVE
2161 #define OPTION_NODE_INTERLEAVE FALSE
2162 #endif
2163 // Ensure that at least one write leveling option is selected
2164 #if OPTION_DDR3 == TRUE
2165 #if OPTION_HW_WRITE_LEV_TRAINING == FALSE
2166 #if OPTION_SW_WRITE_LEV_TRAINING == FALSE
2167 #error No Write leveling option selected for DDR3
2168 #endif
2169 #endif
2170 #if OPTION_SW_DRAM_INIT == FALSE
2171 #error Software dram init must be enabled for DDR3 dimms
2172 #endif
2173 #endif
2174 // Ensure at least one DQS receiver training option is selected
2175 #if OPTION_HW_DQS_REC_EN_TRAINING == FALSE
2176 #if OPTION_NON_OPT_SW_DQS_REC_EN_TRAINING == FALSE
2177 #if OPTION_OPT_SW_DQS_REC_EN_TRAINING == FALSE
2178 #error No DQS receiver training option has been slected
2179 #endif
2180 #endif
2181 #endif
2182 // Ensure at least one Rd Wr position training option has been selected
2183 #if OPTION_NON_OPT_SW_RD_WR_POS_TRAINING == FALSE
2184 #if OPTION_OPT_SW_RD_WR_POS_TRAINING == FALSE
2185 #error No Rd Wr position training option has been selected
2186 #endif
2187 #endif
2188 // Ensure at least one dram init option has been selected
2189 #if OPTION_HW_DRAM_INIT == FALSE
2190 #if OPTION_SW_DRAM_INIT == FALSE
2191 #error No Dram init option has been selected
2192 #endif
2193 #endif
2194 // Ensure the frequency limit is valid
2195 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1866_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 933)
2196 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1600_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 800)
2197 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1333_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 667)
2198 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR1066_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 533)
2199 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR800_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 400)
2200 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR667_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 333)
2201 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR533_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 266)
2202 #if (CFG_MEMORY_BUS_FREQUENCY_LIMIT != DDR400_FREQUENCY) && (CFG_MEMORY_BUS_FREQUENCY_LIMIT != 200)
2203 #error BLDCFG: Unsupported memory bus frequency
2204 #endif
2205 #endif
2206 #endif
2207 #endif
2208 #endif
2209 #endif
2210 #endif
2211 #endif
2212 // Ensure timing mode is valid
2213 #if CFG_TIMING_MODE_SELECT != TIMING_MODE_SPECIFIC
2214 #if CFG_TIMING_MODE_SELECT != TIMING_MODE_LIMITED
2215 #if CFG_TIMING_MODE_SELECT != TIMING_MODE_AUTO
2216 #error BLDCFG: Invalid timing mode is set
2217 #endif
2218 #endif
2219 #endif
2220 // Ensure the scrub rate is valid
2221 #if ((CFG_SCRUB_DRAM_RATE > 0x16) && (CFG_SCRUB_DRAM_RATE != 0xFF))
2222 #error BLDCFG: Unsupported dram scrub rate set
2223 #endif
2224 #if CFG_SCRUB_L2_RATE > 0x16
2225 #error BLDCFG: Unsupported L2 scrubber rate set
2226 #endif
2227 #if CFG_SCRUB_L3_RATE > 0x16
2228 #error BLDCFG: unsupported L3 scrubber rate set
2229 #endif
2230 #if CFG_SCRUB_IC_RATE > 0x16
2231 #error BLDCFG: Unsupported Instruction cache scrub rate set
2232 #endif
2233 #if CFG_SCRUB_DC_RATE > 0x16
2234 #error BLDCFG: Unsupported Dcache scrub rate set
2235 #endif
2236 // Ensure Quad rank dimm type is valid
2237 #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_UNBUFFERED
2238 #if CFG_MEMORY_QUADRANK_TYPE != QUADRANK_REGISTERED
2239 #error BLDCFG: Invalid quad rank dimm type set
2240 #endif
2241 #endif
2242 // Ensure ECC symbol size is valid
2243 #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_USE_BKDG
2244 #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X4
2245 #if CFG_ECC_SYMBOL_SIZE != ECCSYMBOLSIZE_FORCE_X8
2246 #error BLDCFG: Invalid Ecc symbol size set
2247 #endif
2248 #endif
2249 #endif
2250 // Ensure power down mode is valid
2251 #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHIP_SELECT
2252 #if CFG_POWER_DOWN_MODE != POWER_DOWN_BY_CHANNEL
2253 #error BLDCFG: Invalid power down mode set
2254 #endif
2255 #endif
2257 /*****************************************************************************
2258 *
2259 * Process the option logic, setting local control variables
2260 *
2261 ****************************************************************************/
2262 #if OPTION_ACPI_PSTATES == TRUE
2263 #define OPTFCN_ACPI_TABLES CreateAcpiTablesMain
2264 #define OPTFCN_GATHER_DATA PStateGatherData
2265 #if OPTION_MULTISOCKET == TRUE
2266 #define OPTFCN_PSTATE_LEVELING PStateLeveling
2267 #else
2268 #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess
2269 #endif
2270 #else
2271 #define OPTFCN_ACPI_TABLES CommonReturnAgesaSuccess
2272 #define OPTFCN_GATHER_DATA CommonReturnAgesaSuccess
2273 #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess
2274 #endif
2277 /*****************************************************************************
2278 *
2279 * Include the structure definitions for the defaults table structures
2280 *
2281 ****************************************************************************/
2312 /*****************************************************************************
2313 *
2314 * Generate the output structures (defaults tables)
2315 *
2316 ****************************************************************************/
2318 FCH_PLATFORM_POLICY FchUserOptions = {
2362 CFG_FCH_GPIO_CONTROL_LIST // *CfgFchGpioControl
2363 };
2365 BUILD_OPT_CFG UserOptions = {
2371 },
2372 //Build Option Area
2393 //Build Configuration Area
2394 CFG_PCI_MMIO_BASE,
2395 CFG_PCI_MMIO_SIZE,
2396 {
2397 // CoreVrm
2398 {
2404 CFG_VRM_INRUSH_CURRENT_LIMIT // VrmInrushCurrentLimit
2405 },
2406 // NbVrm
2407 {
2413 CFG_VRM_NB_INRUSH_CURRENT_LIMIT // VrmNbInrushCurrentLimit
2414 }
2415 },
2429 {
2434 CFG_USE_VARIABLE_MCT_ISOC_PRIORITY, // The Memory controller will be set to Variable Isoc Priority.
2435 // ADVANCED_PERFORMANCE_PROFILE
2436 {
2439 CFG_PERFORMANCE_DRAM_PREFETCHER // Dram prefetcher mode
2440 },
2441 CFG_PLATFORM_POWER_POLICY_MODE // The platform's power policy mode.
2442 },
2516 {{
2522 }},
2527 (IOMMU_EXCLUSION_RANGE_DESCRIPTOR *) CFG_IOMMU_EXCLUSION_RANGE_LIST, // CfgIvrsExclusionRangeList
2529 };
2531 CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] =
2532 {
2533 #if AGESA_ENTRY_INIT_RESET == TRUE
2538 AMD_INIT_RESET_HANDLE
2539 },
2540 #endif
2542 #if AGESA_ENTRY_INIT_RECOVERY == TRUE
2547 AMD_INIT_POST_HANDLE
2548 },
2549 #endif
2551 #if AGESA_ENTRY_INIT_EARLY == TRUE
2556 AMD_INIT_EARLY_HANDLE
2557 },
2558 #endif
2560 #if AGESA_ENTRY_INIT_ENV == TRUE
2565 AMD_INIT_ENV_HANDLE
2566 },
2567 #endif
2569 #if AGESA_ENTRY_INIT_LATE == TRUE
2574 AMD_INIT_LATE_HANDLE
2575 },
2576 #endif
2578 #if AGESA_ENTRY_INIT_MID == TRUE
2583 AMD_INIT_MID_HANDLE
2584 },
2585 #endif
2587 #if AGESA_ENTRY_INIT_POST == TRUE
2592 AMD_INIT_POST_HANDLE
2593 },
2594 #endif
2596 #if AGESA_ENTRY_INIT_RESUME == TRUE
2601 AMD_INIT_RESUME_HANDLE
2602 },
2603 #endif
2605 #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
2610 AMD_S3_LATE_RESTORE_HANDLE
2611 },
2612 #endif
2614 #if AGESA_ENTRY_INIT_S3SAVE == TRUE
2619 AMD_S3_SAVE_HANDLE
2620 },
2621 #endif
2623 #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
2628 AMD_LATE_RUN_AP_TASK_HANDLE
2629 },
2630 #endif
2632 };
2636 CONST DISPATCH_TABLE ROMDATA DispatchTable[] =
2637 {
2641 #if AGESA_ENTRY_INIT_RESET == TRUE
2643 #endif
2645 #if AGESA_ENTRY_INIT_RECOVERY == TRUE
2647 #endif
2649 #if AGESA_ENTRY_INIT_EARLY == TRUE
2651 #endif
2653 #if AGESA_ENTRY_INIT_POST == TRUE
2655 #endif
2657 #if AGESA_ENTRY_INIT_ENV == TRUE
2659 #endif
2661 #if AGESA_ENTRY_INIT_MID == TRUE
2663 #endif
2665 #if AGESA_ENTRY_INIT_LATE == TRUE
2667 #endif
2669 #if AGESA_ENTRY_INIT_S3SAVE == TRUE
2671 #endif
2673 #if AGESA_ENTRY_INIT_RESUME == TRUE
2675 #endif
2677 #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
2679 #endif
2681 #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
2688 #endif
2690 #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE
2692 #endif
2694 };
2696 CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] =
2697 {
2698 IDS_LATE_RUN_AP_TASK
2699 // Get DMI info
2700 CPU_DMI_AP_GET_TYPE4_TYPE7
2701 // Probe filter enable
2702 L3_FEAT_AP_DISABLE_CACHE
2703 L3_FEAT_AP_ENABLE_CACHE
2704 // Cpu Late Init
2705 CPU_LATE_INIT_AP_TASK
2707 };
2709 #if AGESA_ENTRY_INIT_EARLY == TRUE
2710 #if IDSOPT_IDS_ENABLED == TRUE
2711 #if IDSOPT_TRACING_ENABLED == TRUE
2712 #define MAKE_DBG_STR(x, y) MAKE_AS_A_STRING(x : y)
2714 #if IDS_TRACE_SHOW_BLD_OPT_CFG == TRUE
2715 //Build Option Area
2723 //MAKE_DBG_STR (\nOptParallelTraining, OPTION_PARALLEL_TRAINING)
2735 //Build Configuration Area
2736 // CoreVrm
2743 // NbVrm
2861 #endif
2862 NULL
2863 };
2864 #endif
2865 #endif
2866 #endif