src/mainboard/tyan/s8226/OemCustomize.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <northbridge/amd/agesa/agesawrapper.h>
  17 #include <PlatformMemoryConfiguration.h>
  18
  19 /*----------------------------------------------------------------------------------------
  20  *                        CUSTOMER OVERIDES MEMORY TABLE
  21  *----------------------------------------------------------------------------------------
  22  */
  23
  24 //reference BKDG Table87: works
  25 #define F15_WL_SEED 0x3B //family15 BKDG recommand 3B RDIMM, 1A UDIMM.
  26 #define SEED_A 0x54
  27 #define SEED_B 0x4D
  28 #define SEED_C 0x45
  29 #define SEED_D 0x40
  30
  31 #define F10_WL_SEED 0x3B //family10 BKDG recommand 3B RDIMM, 1A UDIMM.
  32 //4B 41 51
  33
  34 /*
  35  *  Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
  36  *  (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
  37  *  is populated, AGESA will base its settings on the data from the table. Otherwise, it will
  38  *  use its default conservative settings.
  39  */
  40 CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
  41
  42         WRITE_LEVELING_SEED(
  43                         ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS,
  44                         F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED,
  45                         F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED,
  46                         F15_WL_SEED),
  47
  48         HW_RXEN_SEED(
  49                 ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
  50                 SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
  51                 SEED_A),
  52         HW_RXEN_SEED(
  53                 ANY_SOCKET, CHANNEL_B, ALL_DIMMS,
  54                 SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B,
  55                 SEED_B),
  56         HW_RXEN_SEED(
  57                 ANY_SOCKET, CHANNEL_C, ALL_DIMMS,
  58                 SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C,
  59                 SEED_C),
  60         HW_RXEN_SEED(
  61                 ANY_SOCKET, CHANNEL_D, ALL_DIMMS,
  62                 SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D,
  63                 SEED_D),
  64
  65         NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 3), //max 3
  66         PSO_END
  67 };
  68
  69 const struct OEM_HOOK OemCustomize = {
  70 };