src/mainboard/amd/torpedo/OemCustomize.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2011 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include "PlatformGnbPcieComplex.h"
  17
  18 #include <string.h>
  19 #include <northbridge/amd/agesa/agesawrapper.h>
  20 #include <vendorcode/amd/agesa/f12/Proc/CPU/heapManager.h>
  21 #include <PlatformMemoryConfiguration.h>
  22
  23 #define FILECODE PROC_GNB_PCIE_FAMILY_0X12_F12PCIECOMPLEXCONFIG_FILECODE
  24
  25 static const PCIe_PORT_DESCRIPTOR PortList [] = {
  26                         // Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...)
  27                         {
  28                           0,
  29                           PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15),
  30                           PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT2)
  31                         },
  32                         // Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...)
  33                         {
  34                           0,
  35                           PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 19),
  36                           PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT3)
  37                         },
  38                         // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
  39                         {
  40                           0,
  41                           PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
  42                           PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
  43                         },
  44                         // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...)
  45                         {
  46                           0,
  47                           PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5),
  48                           PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
  49                         },
  50                         // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...)
  51                         {
  52                           0,
  53                           PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
  54                           PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
  55                         },
  56                         // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...)
  57                         {
  58                           DESCRIPTOR_TERMINATE_LIST,
  59                           PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
  60                           PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
  61                         }
  62                         // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...)
  63 //                      {
  64 //                        DESCRIPTOR_TERMINATE_LIST,
  65 //                        PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 8),
  66 //                        PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
  67 //                      }
  68 };
  69
  70 static const PCIe_DDI_DESCRIPTOR DdiList [] = {
  71                         // Initialize Ddi descriptor (DDI interface Lanes 24:27, DdA, ...)
  72                         {
  73                           0,
  74                           PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27),
  75                           PCIE_DDI_DATA_INITIALIZER (ConnectorTypeNutmegDpToVga, Aux2, Hdp2)
  76                         },
  77                         // Initialize Ddi descriptor (DDI interface Lanes 28:31, DdB, ...)
  78                         {
  79                           DESCRIPTOR_TERMINATE_LIST,
  80                           PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31),
  81                           PCIE_DDI_DATA_INITIALIZER (ConnectorTypeEDP, Aux1, Hdp1)
  82                         }
  83 };
  84
  85 static const PCIe_COMPLEX_DESCRIPTOR Llano = {
  86         DESCRIPTOR_TERMINATE_LIST,
  87         0,
  88         &PortList[0],
  89         &DdiList[0]
  90 };
  91
  92 /*---------------------------------------------------------------------------------------*/
  93 /**
  94  *  OemCustomizeInitEarly
  95  *
  96  *  Description:
  97  *    This stub function will call the host environment through the binary block
  98  *    interface (call-out port) to provide a user hook opportunity
  99  *
 100  *  Parameters:
 101  *    @param[in]      *InitEarly
 102  *
 103  *    @retval         VOID
 104  *
 105  **/
 106 /*---------------------------------------------------------------------------------------*/
 107
 108 static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
 109 {
 110   AGESA_STATUS         Status;
 111   VOID                 *LlanoPcieComplexListPtr;
 112   VOID                 *LlanoPciePortPtr;
 113   VOID                 *LlanoPcieDdiPtr;
 114
 115   ALLOCATE_HEAP_PARAMS AllocHeapParams;
 116
 117   // GNB PCIe topology Porting
 118
 119   //
 120   // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
 121   //
 122   AllocHeapParams.RequestedBufferSize = sizeof(Llano) + sizeof(PortList) + sizeof(DdiList);
 123
 124   AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
 125   AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
 126   Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
 127         ASSERT(Status == AGESA_SUCCESS);
 128
 129   LlanoPcieComplexListPtr  =  (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
 130
 131   AllocHeapParams.BufferPtr += sizeof(Llano);
 132   LlanoPciePortPtr         =  (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
 133
 134   AllocHeapParams.BufferPtr += sizeof(PortList);
 135   LlanoPcieDdiPtr          =  (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
 136
 137   LibAmdMemFill (LlanoPcieComplexListPtr,
 138                    0,
 139                    sizeof(Llano),
 140                    &InitEarly->StdHeader);
 141
 142   LibAmdMemFill (LlanoPciePortPtr,
 143                    0,
 144                    sizeof(PortList),
 145                    &InitEarly->StdHeader);
 146
 147   LibAmdMemFill (LlanoPcieDdiPtr,
 148                    0,
 149                    sizeof(DdiList),
 150                    &InitEarly->StdHeader);
 151
 152   LibAmdMemCopy  (LlanoPcieComplexListPtr, &Llano, sizeof(Llano), &InitEarly->StdHeader);
 153   LibAmdMemCopy  (LlanoPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader);
 154   LibAmdMemCopy  (LlanoPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader);
 155
 156
 157   ((PCIe_COMPLEX_DESCRIPTOR*)LlanoPcieComplexListPtr)->PciePortList =  (PCIe_PORT_DESCRIPTOR*)LlanoPciePortPtr;
 158   ((PCIe_COMPLEX_DESCRIPTOR*)LlanoPcieComplexListPtr)->DdiLinkList  =  (PCIe_DDI_DESCRIPTOR*)LlanoPcieDdiPtr;
 159
 160   InitEarly->GnbConfig.PcieComplexList = LlanoPcieComplexListPtr;
 161   InitEarly->GnbConfig.PsppPolicy      = 0;
 162         return AGESA_SUCCESS;
 163 }
 164
 165 /*----------------------------------------------------------------------------------------
 166  *                        CUSTOMER OVERIDES MEMORY TABLE
 167  *----------------------------------------------------------------------------------------
 168  */
 169
 170 /*
 171  *  Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
 172  *  (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
 173  *  is populated, AGESA will base its settings on the data from the table. Otherwise, it will
 174  *  use its default conservative settings.
 175  */
 176 CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
 177   NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1),
 178   NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2),
 179   PSO_END
 180 };
 181
 182 const struct OEM_HOOK OemCustomize = {
 183         .InitEarly = OemInitEarly,
 184 };