src/mainboard/tyan/s2912_fam10/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 AMD
   5  * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #define FAM10_SCAN_PCI_BUS 0
  19 #define FAM10_ALLOCATE_IO_RANGE 1
  20
  21 #include <stdint.h>
  22 #include <string.h>
  23 #include <device/pci_def.h>
  24 #include <device/pci_ids.h>
  25 #include <arch/io.h>
  26 #include <device/pnp_def.h>
  27 #include <cpu/x86/lapic.h>
  28 #include <console/console.h>
  29 #include <timestamp.h>
  30 #include <lib.h>
  31 #include <spd.h>
  32 #include <cpu/amd/model_10xxx_rev.h>
  33 #include <delay.h>
  34 #include <cpu/x86/lapic.h>
  35 #include <cpu/amd/car.h>
  36 #include <superio/winbond/common/winbond.h>
  37 #include <superio/winbond/w83627hf/w83627hf.h>
  38 #include <cpu/x86/bist.h>
  39 #include <northbridge/amd/amdfam10/raminit.h>
  40 #include <northbridge/amd/amdht/ht_wrapper.h>
  41 #include <cpu/amd/family_10h-family_15h/init_cpus.h>
  42 #include <arch/early_variables.h>
  43 #include <cbmem.h>
  44 #include <southbridge/nvidia/mcp55/mcp55.h>
  45
  46 #include "resourcemap.c"
  47 #include "cpu/amd/quadcore/quadcore.c"
  48
  49 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  50
  51 void activate_spd_rom(const struct mem_controller *ctrl);
  52 int spd_read_byte(unsigned device, unsigned address);
  53 extern struct sys_info sysinfo_car;
  54
  55 void activate_spd_rom(const struct mem_controller *ctrl) { }
  56
  57 inline int spd_read_byte(unsigned device, unsigned address)
  58 {
  59         return smbus_read_byte(device, address);
  60 }
  61
  62 #define MCP55_MB_SETUP \
  63         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
  64         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
  65         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \
  66         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \
  67         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
  68         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
  69
  70 #include <southbridge/nvidia/mcp55/early_setup_ss.h>
  71 #include "southbridge/nvidia/mcp55/early_setup_car.c"
  72
  73 unsigned get_sbdn(unsigned bus)
  74 {
  75         pci_devfn_t dev;
  76
  77         /* Find the device. */
  78         dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
  79                                        PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
  80
  81         return (dev >> 15) & 0x1f;
  82 }
  83
  84 static void sio_setup(void)
  85 {
  86         uint32_t dword;
  87         uint8_t byte;
  88
  89         byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
  90         byte |= 0x20;
  91         pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
  92
  93         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
  94         /*serial 0 */
  95         dword |= (1 << 0);
  96         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
  97
  98         dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
  99         dword |= (1 << 16);
 100         pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
 101 }
 102
 103 static const u8 spd_addr[] = {
 104         //first node
 105         RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
 106 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 107         //second node
 108         RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0,
 109 #endif
 110 };
 111
 112 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 113 {
 114         struct sys_info *sysinfo = &sysinfo_car;
 115
 116         u32 bsp_apicid = 0, val, wants_reset;
 117         msr_t msr;
 118
 119         timestamp_init(timestamp_get());
 120         timestamp_add_now(TS_START_ROMSTAGE);
 121
 122         if (!cpu_init_detectedx && boot_cpu()) {
 123                 /* Nothing special needs to be done to find bus 0 */
 124                 /* Allow the HT devices to be found */
 125                 set_bsp_node_CHtExtNodeCfgEn();
 126                 enumerate_ht_chain();
 127                 sio_setup();
 128         }
 129
 130         post_code(0x30);
 131
 132         if (bist == 0)
 133                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 134
 135         post_code(0x32);
 136
 137         winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 138         console_init();
 139
 140         /* Halt if there was a built in self test failure */
 141         report_bist_failure(bist);
 142
 143         val = cpuid_eax(1);
 144         printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
 145         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 146         printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
 147         printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 148
 149         /* Setup sysinfo defaults */
 150         set_sysinfo_in_ram(0);
 151
 152         update_microcode(val);
 153
 154         post_code(0x33);
 155
 156         cpuSetAMDMSR(0);
 157         post_code(0x34);
 158
 159         amd_ht_init(sysinfo);
 160         post_code(0x35);
 161
 162         /* Setup nodes PCI space and start core 0 AP init. */
 163         finalize_node_setup(sysinfo);
 164
 165         /* Setup any mainboard PCI settings etc. */
 166         setup_mb_resource_map();
 167         post_code(0x36);
 168
 169         /* wait for all the APs core0 started by finalize_node_setup. */
 170         /* FIXME: A bunch of cores are going to start output to serial at once.
 171          * It would be nice to fixup prink spinlocks for ROM XIP mode.
 172          * I think it could be done by putting the spinlock flag in the cache
 173          * of the BSP located right after sysinfo.
 174          */
 175         wait_all_core0_started();
 176
 177 #if IS_ENABLED(CONFIG_LOGICAL_CPUS)
 178         /* Core0 on each node is configured. Now setup any additional cores. */
 179         printk(BIOS_DEBUG, "start_other_cores()\n");
 180         start_other_cores(bsp_apicid);
 181         post_code(0x37);
 182         wait_all_other_cores_started(bsp_apicid);
 183 #endif
 184
 185         post_code(0x38);
 186
 187 #if IS_ENABLED(CONFIG_SET_FIDVID)
 188         msr = rdmsr(0xc0010071);
 189         printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 190
 191         /* FIXME: The sb fid change may survive the warm reset and only
 192          * need to be done once.*/
 193         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 194
 195         post_code(0x39);
 196
 197         if (!warm_reset_detect(0)) {                    // BSP is node 0
 198                 init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
 199         } else {
 200                 init_fidvid_stage2(bsp_apicid, 0);      // BSP is node 0
 201         }
 202
 203         post_code(0x3A);
 204
 205         /* show final fid and vid */
 206         msr = rdmsr(0xc0010071);
 207         printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 208 #endif
 209
 210         init_timer(); // Need to use TMICT to synchronize FID/VID
 211
 212         wants_reset = mcp55_early_setup_x();
 213
 214         /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
 215         if (!warm_reset_detect(0)) {
 216                 printk(BIOS_INFO, "...WARM RESET...\n\n\n");
 217                 soft_reset();
 218                 die("After soft_reset_x - shouldn't see this message!!!\n");
 219         }
 220
 221         if (wants_reset)
 222                 printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n");
 223
 224         post_code(0x3B);
 225
 226         /* It's the time to set ctrl in sysinfo now; */
 227         printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
 228         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 229         post_code(0x3D);
 230
 231         printk(BIOS_DEBUG, "enable_smbus()\n");
 232         enable_smbus();
 233
 234         post_code(0x40);
 235
 236         timestamp_add_now(TS_BEFORE_INITRAM);
 237         printk(BIOS_DEBUG, "raminit_amdmct()\n");
 238         raminit_amdmct(sysinfo);
 239         timestamp_add_now(TS_AFTER_INITRAM);
 240
 241         cbmem_initialize_empty();
 242         post_code(0x41);
 243
 244         amdmct_cbmem_store_info(sysinfo);
 245
 246 }
 247
 248 /**
 249  * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
 250  * Description:
 251  *      This routine is called every time a non-coherent chain is processed.
 252  *      BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
 253  *      swap list. The first part of the list controls the BUID assignment and the
 254  *      second part of the list provides the device to device linking.  Device orientation
 255  *      can be detected automatically, or explicitly.  See documentation for more details.
 256  *
 257  *      Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
 258  *      based on each device's unit count.
 259  *
 260  * Parameters:
 261  *      @param[in]  node   = The node on which this chain is located
 262  *      @param[in]  link   = The link on the host for this chain
 263  *      @param[out] List   = supply a pointer to a list
 264  */
 265 BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
 266 {
 267         static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
 268         /* If the BUID was adjusted in early_ht we need to do the manual override */
 269         if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
 270                 printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
 271                 if ((node == 0) && (link == 0)) {       /* BSP SB link */
 272                         *List = swaplist;
 273                         return 1;
 274                 }
 275         }
 276
 277         return 0;
 278 }