src/mainboard/hp/dl165_g6_fam10/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2006 Tyan
   5  * Copyright (C) 2006 AMD
   6  * Written by Yinghai Lu <yinghailu@gmail.com> for Tyan and AMD.
   7  *
   8  * Copyright (C) 2007 University of Mannheim
   9  * Written by Philipp Degler <pdegler@rumms.uni-mannheim.de> for University of Mannheim
  10  * Copyright (C) 2009 University of Heidelberg
  11  * Written by Mondrian Nuessle <nuessle@uni-heidelberg.de> for University of Heidelberg
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  */
  23
  24 #define FAM10_SCAN_PCI_BUS 0
  25 #define FAM10_ALLOCATE_IO_RANGE 1
  26
  27 #include <stdint.h>
  28 #include <string.h>
  29 #include <device/pci_def.h>
  30 #include <device/pci_ids.h>
  31 #include <arch/io.h>
  32 #include <device/pnp_def.h>
  33 #include <cpu/x86/lapic.h>
  34 #include "option_table.h"
  35 #include <console/console.h>
  36 #include <timestamp.h>
  37 #include <cpu/amd/model_10xxx_rev.h>
  38 #include <lib.h>
  39 #include <spd.h>
  40 #include <delay.h>
  41 #include <cpu/x86/lapic.h>
  42 #include <superio/serverengines/pilot/pilot.h>
  43 #include <superio/nsc/pc87417/pc87417.h>
  44 #include <cpu/x86/bist.h>
  45 #include <cpu/amd/car.h>
  46 #include <northbridge/amd/amdfam10/raminit.h>
  47 #include <northbridge/amd/amdht/ht_wrapper.h>
  48 #include <cpu/amd/family_10h-family_15h/init_cpus.h>
  49 #include <arch/early_variables.h>
  50 #include <cbmem.h>
  51 #include "southbridge/broadcom/bcm5785/early_smbus.c"
  52 #include "southbridge/broadcom/bcm5785/early_setup.c"
  53
  54 #include "cpu/amd/quadcore/quadcore.c"
  55
  56 #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
  57 #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)
  58
  59 void activate_spd_rom(const struct mem_controller *ctrl);
  60 int spd_read_byte(unsigned device, unsigned address);
  61 extern struct sys_info sysinfo_car;
  62
  63 inline void activate_spd_rom(const struct mem_controller *ctrl)
  64 {
  65         u8 val;
  66         outb(0x3d, 0x0cd6);
  67         outb(0x87, 0x0cd7);
  68
  69         outb(0x44, 0xcd6);
  70         val = inb(0xcd7);
  71         outb((val & ~3) | ctrl->spd_switch_addr, 0xcd7);
  72 }
  73
  74 inline int spd_read_byte(unsigned device, unsigned address)
  75 {
  76         return smbus_read_byte(device, address);
  77 }
  78
  79 static const u8 spd_addr[] = {
  80         // switch addr, 1A addr, 2A addr, 3A addr, 4A addr, 1B addr, 2B addr, 3B addr 4B addr
  81         //first node
  82         RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
  83 #if CONFIG_MAX_PHYSICAL_CPUS > 1
  84         //second node
  85         RC01, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
  86 #endif
  87 };
  88
  89 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  90 {
  91         struct sys_info *sysinfo = &sysinfo_car;
  92         u32 bsp_apicid = 0, val;
  93         msr_t msr;
  94
  95         timestamp_init(timestamp_get());
  96         timestamp_add_now(TS_START_ROMSTAGE);
  97
  98         if (!cpu_init_detectedx && boot_cpu()) {
  99                 /* Nothing special needs to be done to find bus 0 */
 100                 /* Allow the HT devices to be found */
 101                 /* mov bsp to bus 0xff when > 8 nodes */
 102                 set_bsp_node_CHtExtNodeCfgEn();
 103                 enumerate_ht_chain();
 104                 bcm5785_enable_lpc();
 105                 pc87417_enable_dev(RTC_DEV); /* Enable RTC */
 106         }
 107
 108         post_code(0x30);
 109
 110         if (bist == 0)
 111                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 112
 113         pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 114
 115         console_init();
 116
 117         /* Halt if there was a built in self test failure */
 118         report_bist_failure(bist);
 119
 120         pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV
 121
 122         val = cpuid_eax(1);
 123         printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
 124         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 125         printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
 126         printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 127
 128         /* Setup sysinfo defaults */
 129         set_sysinfo_in_ram(0);
 130
 131         update_microcode(val);
 132
 133         post_code(0x33);
 134
 135         cpuSetAMDMSR(0);
 136         post_code(0x34);
 137
 138         amd_ht_init(sysinfo);
 139         post_code(0x35);
 140
 141         /* Setup nodes PCI space and start core 0 AP init. */
 142         finalize_node_setup(sysinfo);
 143
 144         post_code(0x36);
 145
 146         /* wait for all the APs core0 started by finalize_node_setup. */
 147         /* FIXME: A bunch of cores are going to start output to serial at once.
 148          * It would be nice to fixup prink spinlocks for ROM XIP mode.
 149          * I think it could be done by putting the spinlock flag in the cache
 150          * of the BSP located right after sysinfo.
 151          */
 152
 153         wait_all_core0_started();
 154
 155 #if IS_ENABLED(CONFIG_LOGICAL_CPUS)
 156         /* Core0 on each node is configured. Now setup any additional cores. */
 157         printk(BIOS_DEBUG, "start_other_cores()\n");
 158         start_other_cores(bsp_apicid);
 159         post_code(0x37);
 160         wait_all_other_cores_started(bsp_apicid);
 161 #endif
 162
 163 #if IS_ENABLED(CONFIG_SET_FIDVID)
 164         msr = rdmsr(0xc0010071);
 165         printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 166
 167         /* FIXME: The sb fid change may survive the warm reset and only
 168          * need to be done once.*/
 169
 170         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 171
 172         post_code(0x39);
 173
 174         if (!warm_reset_detect(0)) {                    // BSP is node 0
 175                 init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
 176         } else {
 177                 init_fidvid_stage2(bsp_apicid, 0);      // BSP is node 0
 178         }
 179
 180         post_code(0x3A);
 181
 182         /* show final fid and vid */
 183         msr = rdmsr(0xc0010071);
 184         printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 185 #endif
 186
 187         init_timer();
 188
 189         /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
 190         if (!warm_reset_detect(0)) {
 191                 printk(BIOS_INFO, "...WARM RESET...\n\n\n");
 192                 soft_reset();
 193                 die("After soft_reset_x - shouldn't see this message!!!\n");
 194         }
 195
 196         /* It's the time to set ctrl in sysinfo now; */
 197         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 198         enable_smbus();
 199
 200         //do we need apci timer, tsc...., only debug need it for better output
 201         /* all ap stopped? */
 202 //      init_timer(); // Need to use TMICT to synchronize FID/VID
 203
 204         timestamp_add_now(TS_BEFORE_INITRAM);
 205         printk(BIOS_DEBUG, "raminit_amdmct()\n");
 206         raminit_amdmct(sysinfo);
 207         timestamp_add_now(TS_AFTER_INITRAM);
 208
 209         cbmem_initialize_empty();
 210         post_code(0x41);
 211
 212         amdmct_cbmem_store_info(sysinfo);
 213
 214         bcm5785_early_setup();
 215 }
 216
 217 /**
 218  * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
 219  * Description:
 220  *      This routine is called every time a non-coherent chain is processed.
 221  *      BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
 222  *      swap list. The first part of the list controls the BUID assignment and the
 223  *      second part of the list provides the device to device linking.  Device orientation
 224  *      can be detected automatically, or explicitly.  See documentation for more details.
 225  *
 226  *      Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
 227  *      based on each device's unit count.
 228  *
 229  * Parameters:
 230  *      @param[in]  node   = The node on which this chain is located
 231  *      @param[in]  link   = The link on the host for this chain
 232  *      @param[out] List   = supply a pointer to a list
 233  */
 234 BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
 235 {
 236         static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
 237         /* If the BUID was adjusted in early_ht we need to do the manual override */
 238         if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
 239                 printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
 240                 if ((node == 0) && (link == 0)) {       /* BSP SB link */
 241                         *List = swaplist;
 242                         return 1;
 243                 }
 244         }
 245
 246         return 0;
 247 }