src/mainboard/amd/tilapia_fam10/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2010 Advanced Micro Devices, Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #define SYSTEM_TYPE 1   /* DESKTOP */
  17
  18 /* used by incoherent_ht */
  19 #define FAM10_SCAN_PCI_BUS 0
  20 #define FAM10_ALLOCATE_IO_RANGE 0
  21
  22 #include <stdint.h>
  23 #include <string.h>
  24 #include <device/pci_def.h>
  25 #include <device/pci_ids.h>
  26 #include <arch/io.h>
  27 #include <device/pnp_def.h>
  28 #include <cpu/x86/lapic.h>
  29 #include <console/console.h>
  30 #include <timestamp.h>
  31 #include <cpu/amd/model_10xxx_rev.h>
  32 #include <lib.h>
  33 #include <cpu/x86/lapic.h>
  34 #include <commonlib/loglevel.h>
  35 #include <cpu/x86/bist.h>
  36 #include <superio/ite/common/ite.h>
  37 #include <superio/ite/it8718f/it8718f.h>
  38 #include <cpu/amd/mtrr.h>
  39 #include <cpu/amd/car.h>
  40 #include <southbridge/amd/sb700/sb700.h>
  41 #include <southbridge/amd/sb700/smbus.h>
  42 #include <northbridge/amd/amdfam10/raminit.h>
  43 #include <northbridge/amd/amdht/ht_wrapper.h>
  44 #include <cpu/amd/family_10h-family_15h/init_cpus.h>
  45 #include <arch/early_variables.h>
  46 #include <cbmem.h>
  47 #include <spd.h>
  48 #include "southbridge/amd/rs780/early_setup.c"
  49
  50 #include "resourcemap.c"
  51 #include "cpu/amd/quadcore/quadcore.c"
  52
  53 #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
  54
  55 void activate_spd_rom(const struct mem_controller *ctrl);
  56 int spd_read_byte(unsigned device, unsigned address);
  57 extern struct sys_info sysinfo_car;
  58
  59 void activate_spd_rom(const struct mem_controller *ctrl) { }
  60
  61 int spd_read_byte(u32 device, u32 address)
  62 {
  63         return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
  64 }
  65
  66
  67 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  68 {
  69         struct sys_info *sysinfo = &sysinfo_car;
  70         static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
  71         u32 bsp_apicid = 0, val;
  72         msr_t msr;
  73
  74         timestamp_init(timestamp_get());
  75         timestamp_add_now(TS_START_ROMSTAGE);
  76
  77         if (!cpu_init_detectedx && boot_cpu()) {
  78                 /* Nothing special needs to be done to find bus 0 */
  79                 /* Allow the HT devices to be found */
  80                 /* mov bsp to bus 0xff when > 8 nodes */
  81                 set_bsp_node_CHtExtNodeCfgEn();
  82                 enumerate_ht_chain();
  83                 sb7xx_51xx_pci_port80();
  84         }
  85
  86         post_code(0x30);
  87
  88         if (bist == 0) {
  89                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */
  90                 /* All cores run this but the BSP(node0,core0) is the only core that returns. */
  91         }
  92
  93         post_code(0x32);
  94
  95         enable_rs780_dev8();
  96         sb7xx_51xx_lpc_init();
  97
  98         ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
  99
 100         console_init();
 101
 102         /* Halt if there was a built in self test failure */
 103         report_bist_failure(bist);
 104
 105         /* Load MPB */
 106         val = cpuid_eax(1);
 107         printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
 108         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 109         printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
 110         printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
 111
 112         /* Setup sysinfo defaults */
 113         set_sysinfo_in_ram(0);
 114
 115         update_microcode(val);
 116
 117         post_code(0x33);
 118
 119         cpuSetAMDMSR(0);
 120         post_code(0x34);
 121
 122         amd_ht_init(sysinfo);
 123         post_code(0x35);
 124
 125         /* Setup nodes PCI space and start core 0 AP init. */
 126         finalize_node_setup(sysinfo);
 127
 128         /* Setup any mainboard PCI settings etc. */
 129         setup_mb_resource_map();
 130         post_code(0x36);
 131
 132         /* wait for all the APs core0 started by finalize_node_setup. */
 133         /* FIXME: A bunch of cores are going to start output to serial at once.
 134            It would be nice to fixup prink spinlocks for ROM XIP mode.
 135            I think it could be done by putting the spinlock flag in the cache
 136            of the BSP located right after sysinfo.
 137          */
 138         wait_all_core0_started();
 139
 140 #if IS_ENABLED(CONFIG_LOGICAL_CPUS)
 141         /* Core0 on each node is configured. Now setup any additional cores. */
 142         printk(BIOS_DEBUG, "start_other_cores()\n");
 143         start_other_cores(bsp_apicid);
 144         post_code(0x37);
 145         wait_all_other_cores_started(bsp_apicid);
 146 #endif
 147
 148         post_code(0x38);
 149
 150         /* run _early_setup before soft-reset. */
 151         rs780_early_setup();
 152         sb7xx_51xx_early_setup();
 153
 154 #if IS_ENABLED(CONFIG_SET_FIDVID)
 155         msr = rdmsr(0xc0010071);
 156         printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 157
 158         /* FIXME: The sb fid change may survive the warm reset and only
 159            need to be done once.*/
 160         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 161
 162         post_code(0x39);
 163
 164         if (!warm_reset_detect(0)) {                    /* BSP is node 0 */
 165                 init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
 166         } else {
 167                 init_fidvid_stage2(bsp_apicid, 0);      /* BSP is node 0 */
 168         }
 169
 170         post_code(0x3A);
 171
 172         /* show final fid and vid */
 173         msr = rdmsr(0xc0010071);
 174         printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
 175 #endif
 176
 177         rs780_htinit();
 178
 179         /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
 180         if (!warm_reset_detect(0)) {
 181                 printk(BIOS_INFO, "...WARM RESET...\n\n\n");
 182                 soft_reset();
 183                 die("After soft_reset_x - shouldn't see this message!!!\n");
 184         }
 185
 186         post_code(0x3B);
 187
 188         /* It's the time to set ctrl in sysinfo now; */
 189         printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
 190         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 191
 192         post_code(0x40);
 193
 194         timestamp_add_now(TS_BEFORE_INITRAM);
 195         printk(BIOS_DEBUG, "raminit_amdmct()\n");
 196         raminit_amdmct(sysinfo);
 197         timestamp_add_now(TS_AFTER_INITRAM);
 198
 199         cbmem_initialize_empty();
 200         post_code(0x41);
 201
 202         amdmct_cbmem_store_info(sysinfo);
 203
 204         rs780_before_pci_init();
 205         sb7xx_51xx_before_pci_init();
 206
 207         post_code(0x42);
 208 }
 209
 210 /**
 211  * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List)
 212  * Description:
 213  *      This routine is called every time a non-coherent chain is processed.
 214  *      BUID assignment may be controlled explicitly on a non-coherent chain. Provide a
 215  *      swap list. The first part of the list controls the BUID assignment and the
 216  *      second part of the list provides the device to device linking.  Device orientation
 217  *      can be detected automatically, or explicitly.  See documentation for more details.
 218  *
 219  *      Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially
 220  *      based on each device's unit count.
 221  *
 222  * Parameters:
 223  *      @param[in]  node   = The node on which this chain is located
 224  *      @param[in]  link   = The link on the host for this chain
 225  *      @param[out] List   = supply a pointer to a list
 226  */
 227 BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List)
 228 {
 229         static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF };
 230         /* If the BUID was adjusted in early_ht we need to do the manual override */
 231         if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) {
 232                 printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n");
 233                 if ((node == 0) && (link == 0)) {       /* BSP SB link */
 234                         *List = swaplist;
 235                         return 1;
 236                 }
 237         }
 238
 239         return 0;
 240 }