src/mainboard/amd/serengeti_cheetah/romstage.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <stdint.h>
  15 #include <string.h>
  16 #include <device/pci_def.h>
  17 #include <device/pci_ids.h>
  18 #include <arch/io.h>
  19 #include <device/pnp_def.h>
  20 #include <pc80/mc146818rtc.h>
  21 #include <console/console.h>
  22 #include <cpu/amd/model_fxx_rev.h>
  23 #include "southbridge/amd/amd8111/early_smbus.c"
  24 #include <reset.h>
  25 #include <northbridge/amd/amdk8/raminit.h>
  26 #include <cpu/amd/car.h>
  27 #include <cpu/x86/bist.h>
  28 #include <delay.h>
  29
  30 #include <cpu/amd/mtrr.h>
  31 #include <superio/winbond/common/winbond.h>
  32 #include <superio/winbond/w83627hf/w83627hf.h>
  33 #include "northbridge/amd/amdk8/setup_resource_map.c"
  34 #include <northbridge/amd/amdk8/f.h>
  35
  36 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  37
  38 unsigned get_sbdn(unsigned bus);
  39
  40 static void memreset_setup(void)
  41 {
  42         /* GPIO on amd8111 to enable MEMRST ???? */
  43         outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16);  /* REVC_MEMRST_EN = 1 */
  44         outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17);
  45 }
  46
  47 void memreset(int controllers, const struct mem_controller *ctrl) { }
  48
  49 void activate_spd_rom(const struct mem_controller *ctrl)
  50 {
  51 #define SMBUS_HUB 0x18
  52         int ret,i;
  53         unsigned device=(ctrl->channel0[0])>>8;
  54         /* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time */
  55         i = 2;
  56         do {
  57                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
  58         } while ((ret != 0) && (i-->0));
  59
  60         smbus_write_byte(SMBUS_HUB, 0x03, 0);
  61 }
  62
  63 int spd_read_byte(unsigned int device, unsigned int address)
  64 {
  65         return smbus_read_byte(device, address);
  66 }
  67
  68 #include "southbridge/amd/amd8111/early_ctrl.c"
  69 #include <northbridge/amd/amdk8/amdk8.h>
  70 #include "northbridge/amd/amdk8/incoherent_ht.c"
  71 #include "lib/generic_sdram.c"
  72 #include "resourcemap.c"
  73 #include "cpu/amd/dualcore/dualcore.c"
  74 #include <spd.h>
  75 #include "cpu/amd/model_fxx/init_cpus.c"
  76 #include "cpu/amd/model_fxx/fidvid.c"
  77
  78 #define RC0 ((1 << 0)<<8)
  79 #define RC1 ((1 << 1)<<8)
  80 #define RC2 ((1 << 2)<<8)
  81 #define RC3 ((1 << 3)<<8)
  82
  83 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  84 {
  85         static const uint16_t spd_addr[] = {
  86                         /* first node */
  87                         RC0|DIMM0, RC0|DIMM2, 0, 0,
  88                         RC0|DIMM1, RC0|DIMM3, 0, 0,
  89 #if CONFIG_MAX_PHYSICAL_CPUS > 1
  90                         /* second node */
  91                         RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6,
  92                         RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7,
  93 #endif
  94 #if CONFIG_MAX_PHYSICAL_CPUS > 2
  95                         /*  third node */
  96                         RC2|DIMM0, RC2|DIMM2, 0, 0,
  97                         RC2|DIMM1, RC2|DIMM3, 0, 0,
  98                         /*  four node */
  99                         RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6,
 100                         RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7,
 101 #endif
 102
 103         };
 104
 105         struct sys_info *sysinfo = &sysinfo_car;
 106         int needs_reset;
 107         unsigned bsp_apicid = 0;
 108 #if IS_ENABLED(CONFIG_SET_FIDVID)
 109         struct cpuid_result cpuid1;
 110 #endif
 111
 112         if (bist == 0)
 113                 bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 114
 115         winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 116         console_init();
 117
 118         /* Halt if there was a built in self test failure */
 119         report_bist_failure(bist);
 120
 121         printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
 122
 123         setup_mb_resource_map();
 124
 125         printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
 126
 127         set_sysinfo_in_ram(0); /* in BSP so could hold all ap until sysinfo is in ram */
 128         setup_coherent_ht_domain(); /* routing table and start other core0 */
 129
 130         wait_all_core0_started();
 131 #if IS_ENABLED(CONFIG_LOGICAL_CPUS)
 132         /* It is said that we should start core1 after all core0 launched */
 133         /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
 134          * So here need to make sure last core0 is started, esp for two way system,
 135          * (there may be apic id conflicts in that case)
 136          */
 137         start_other_cores();
 138         wait_all_other_cores_started(bsp_apicid);
 139 #endif
 140
 141         /* it will set up chains and store link pair for optimization later */
 142         ht_setup_chains_x(sysinfo); /* it will init sblnk and sbbusn, nodes, sbdn */
 143
 144 #if IS_ENABLED(CONFIG_SET_FIDVID)
 145         /* Check to see if processor is capable of changing FIDVID  */
 146         /* otherwise it will throw a GP# when reading FIDVID_STATUS */
 147         cpuid1 = cpuid(0x80000007);
 148         if ((cpuid1.edx & 0x6) == 0x6) {
 149
 150         {
 151                 /* Read FIDVID_STATUS */
 152                 msr_t msr;
 153                 msr = rdmsr(0xc0010042);
 154                 printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
 155         }
 156
 157         enable_fid_change();
 158         enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
 159         init_fidvid_bsp(bsp_apicid);
 160
 161         /* show final fid and vid */
 162         {
 163                 msr_t msr;
 164                 msr = rdmsr(0xc0010042);
 165                 printk(BIOS_DEBUG, "end   msr fid, vid %08x%08x\n", msr.hi, msr.lo);
 166         }
 167
 168         } else {
 169                 printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
 170         }
 171 #endif
 172
 173 #if 1
 174         needs_reset = optimize_link_coherent_ht();
 175         needs_reset |= optimize_link_incoherent_ht(sysinfo);
 176
 177         /* fidvid change will issue one LDTSTOP and the HT change will be effective too */
 178         if (needs_reset) {
 179                 printk(BIOS_INFO, "ht reset -\n");
 180                 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
 181         }
 182 #endif
 183         allow_all_aps_stop(bsp_apicid);
 184
 185         /* It's the time to set ctrl in sysinfo now; */
 186         fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
 187
 188         enable_smbus();
 189
 190         memreset_setup();
 191
 192         /* do we need apci timer, tsc...., only debug need it for better output */
 193         /* all ap stopped? */
 194         /* Need to use TMICT to synchronize FID/VID */
 195
 196         sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
 197 }