src/mainboard/msi/ms7135/cache_as_ram_auto.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2007 AMD
   5  * (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
   6  * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
   7  * (Thanks to LSRA University of Mannheim for their support)
   8  * Copyright (C) 2008 Jonathan A. Kollasch <jakllsch@kollasch.net>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  23  */
  24
  25 #define ASSEMBLY 1
  26 #define __ROMCC__
  27
  28 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  29
  30 /* Used by raminit. */
  31 #define QRANK_DIMM_SUPPORT 1
  32
  33 /* Turn this on for SMBus debugging output. */
  34 #define DEBUG_SMBUS 0
  35
  36 #if CONFIG_LOGICAL_CPUS == 1
  37 #define SET_NB_CFG_54 1
  38 #endif
  39
  40 #include <stdint.h>
  41 #include <device/pci_def.h>
  42 #include <arch/io.h>
  43 #include <device/pnp_def.h>
  44 #include <arch/romcc_io.h>
  45 #include <cpu/x86/lapic.h>
  46 #include "option_table.h"
  47 #include "pc80/mc146818rtc_early.c"
  48 #include "cpu/x86/lapic/boot_cpu.c"
  49 #include "northbridge/amd/amdk8/reset_test.c"
  50 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  51
  52 #if USE_FAILOVER_IMAGE == 0
  53
  54 /* Used by ck804_early_setup(). */
  55 #define CK804_NUM 1
  56 #define CK804_USE_NIC 1
  57 #define CK804_USE_ACI 1
  58
  59 #if CONFIG_USE_INIT == 0
  60 #include "lib/memcpy.c"
  61 #endif
  62
  63 #include <cpu/amd/model_fxx_rev.h>
  64 #include "pc80/serial.c"
  65 #include "arch/i386/lib/console.c"
  66 #include "ram/ramtest.c"
  67 #include "northbridge/amd/amdk8/incoherent_ht.c"
  68 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
  69 #include "northbridge/amd/amdk8/raminit.h"
  70 #include "cpu/amd/model_fxx/apic_timer.c"
  71 #include "lib/delay.c"
  72 #include "northbridge/amd/amdk8/debug.c"
  73 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  74 #include "cpu/x86/bist.h"
  75 #include "northbridge/amd/amdk8/setup_resource_map.c"
  76 #include "northbridge/amd/amdk8/coherent_ht.c"
  77 #include "cpu/amd/dualcore/dualcore.c"
  78
  79 static void memreset_setup(void)
  80 {
  81         /* FIXME: Nothing to do? */
  82 }
  83
  84 static void memreset(int controllers, const struct mem_controller *ctrl)
  85 {
  86         /* FIXME: Nothing to do? */
  87 }
  88
  89 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  90 {
  91         /* FIXME: Nothing to do? */
  92 }
  93
  94 static inline int spd_read_byte(unsigned device, unsigned address)
  95 {
  96         return smbus_read_byte(device, address);
  97 }
  98
  99 #include "northbridge/amd/amdk8/raminit.c"
 100 #include "sdram/generic_sdram.c"
 101 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
 102 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
 103 #include "cpu/amd/car/copy_and_run.c"
 104 #include "cpu/amd/car/post_cache_as_ram.c"
 105 #include "cpu/amd/model_fxx/init_cpus.c"
 106
 107 #endif  /* USE_FAILOVER_IMAGE */
 108
 109 #if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) \
 110         || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
 111
 112 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
 113 #include "northbridge/amd/amdk8/early_ht.c"
 114
 115 static void sio_setup(void)
 116 {
 117         unsigned value;
 118         uint32_t dword;
 119         uint8_t byte;
 120
 121         /* Subject decoding */
 122         byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b);
 123         byte |= 0x20;
 124         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0x7b, byte);
 125
 126         /* LPC Positive Decode 0 */
 127         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0);
 128         /* Serial 0, Serial 1 */
 129         dword |= (1 << 0) | (1 << 1);
 130         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE + 1, 0), 0xa0, dword);
 131 }
 132
 133 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 134 {
 135         unsigned last_boot_normal_x = last_boot_normal();
 136
 137         /* Is this a CPU only reset? Or is this a secondary CPU? */
 138         if ((cpu_init_detectedx) || (!boot_cpu())) {
 139                 if (last_boot_normal_x) {
 140                         goto normal_image;
 141                 } else {
 142                         goto fallback_image;
 143                 }
 144         }
 145
 146         /* Nothing special needs to be done to find bus 0 */
 147         /* Allow the HT devices to be found */
 148         enumerate_ht_chain();
 149
 150         sio_setup();
 151
 152         /* Setup the ck804 */
 153         ck804_enable_rom();
 154
 155         /* Is this a deliberate reset by the BIOS? */
 156         if (bios_reset_detected() && last_boot_normal_x) {
 157                 goto normal_image;
 158         }
 159
 160         /* This is the primary CPU. How should I boot? */
 161         else if (do_normal_boot()) {
 162                 goto normal_image;
 163         } else {
 164                 goto fallback_image;
 165         }
 166
 167 normal_image:
 168         __asm__ volatile ("jmp __normal_image"
 169                 :                                       /* outputs */
 170                 :"a" (bist), "b"(cpu_init_detectedx)    /* inputs */
 171                 );
 172
 173 fallback_image:
 174
 175 #if HAVE_FAILOVER_BOOT == 1
 176         __asm__ volatile ("jmp __fallback_image"
 177                 :                                       /* outputs */
 178                 :"a" (bist), "b"(cpu_init_detectedx)    /* inputs */
 179                 )
 180 #endif
 181         ;
 182 }
 183
 184 #endif /* ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) ... */
 185
 186 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 187
 188 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 189 {
 190 #if HAVE_FAILOVER_BOOT == 1
 191 #if USE_FAILOVER_IMAGE == 1
 192         failover_process(bist, cpu_init_detectedx);
 193 #else
 194         real_main(bist, cpu_init_detectedx);
 195 #endif
 196 #else
 197 #if USE_FALLBACK_IMAGE == 1
 198         failover_process(bist, cpu_init_detectedx);
 199 #endif
 200         real_main(bist, cpu_init_detectedx);
 201 #endif
 202 }
 203
 204 #if USE_FAILOVER_IMAGE == 0
 205 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 206 {
 207         static const uint16_t spd_addr[] = {
 208                 (0xa << 3) | 0, (0xa << 3) | 1, 0, 0,
 209                 0, 0, 0, 0,
 210                 0, 0, 0, 0,
 211                 0, 0, 0, 0,
 212         };
 213
 214         int needs_reset;
 215         unsigned bsp_apicid = 0;
 216
 217         struct mem_controller ctrl[8];
 218         unsigned nodes;
 219
 220         if (bist == 0) {
 221                 bsp_apicid = init_cpus(cpu_init_detectedx);
 222         }
 223
 224         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 225         uart_init();
 226         console_init();
 227
 228         /* Halt if there was a built in self test failure */
 229         report_bist_failure(bist);
 230
 231 #if 0
 232         dump_pci_device(PCI_DEV(0, 0x18, 0));
 233 #endif
 234
 235         needs_reset = setup_coherent_ht_domain();
 236
 237         wait_all_core0_started();
 238 #if CONFIG_LOGICAL_CPUS==1
 239         // It is said that we should start core1 after all core0 launched
 240         start_other_cores();
 241         wait_all_other_cores_started(bsp_apicid);
 242 #endif
 243
 244         needs_reset |= ht_setup_chains_x();
 245
 246         needs_reset |= ck804_early_setup_x();
 247
 248         if (needs_reset) {
 249                 print_info("ht reset -\r\n");
 250                 soft_reset();
 251         }
 252
 253         allow_all_aps_stop(bsp_apicid);
 254
 255         nodes = get_nodes();
 256         //It's the time to set ctrl now;
 257         fill_mem_ctrl(nodes, ctrl, spd_addr);
 258
 259         enable_smbus();
 260
 261 #if 0
 262         dump_spd_registers(&ctrl[0]);
 263         dump_smbus_registers();
 264 #endif
 265
 266         memreset_setup();
 267         sdram_initialize(nodes, ctrl);
 268
 269 #if 0
 270         print_pci_devices();
 271         dump_pci_devices();
 272 #endif
 273
 274         post_cache_as_ram();
 275 }
 276 #endif /* USE_FAILOVER_IMAGE */