src/southbridge/intel/common/rcba_pirq.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  * Copyright (C) 2012 The Chromium OS Authors.  All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #ifndef SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ_H
  18 #define SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ_H
  19
  20 /*
  21  * The DnnIR registers use common RCBA offsets across these chipsets:
  22  * bd82x6x, i82801, i89xx, ibexpeak, lynxpoint
  23  *
  24  * However not all registers are in use on all of these.
  25  */
  26
  27 #define D31IR           0x3140  /* 16bit */
  28 #define D30IR           0x3142  /* 16bit */
  29 #define D29IR           0x3144  /* 16bit */
  30 #define D28IR           0x3146  /* 16bit */
  31 #define D27IR           0x3148  /* 16bit */
  32 #define D26IR           0x314c  /* 16bit */
  33 #define D25IR           0x3150  /* 16bit */
  34 #define D23IR           0x3158  /* 16bit */
  35 #define D22IR           0x315c  /* 16bit */
  36 #define D21IR           0x3164  /* 16bit */
  37 #define D20IR           0x3160  /* 16bit */
  38 #define D19IR           0x3168  /* 16bit */
  39
  40 #endif /* SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ_H */