src/northbridge/intel/haswell/haswell_mrc/raminit.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <console/console.h>
   4 #include <console/usb.h>
   5 #include <string.h>
   6 #include <cbmem.h>
   7 #include <cbfs.h>
   8 #include <cf9_reset.h>
   9 #include <ip_checksum.h>
  10 #include <memory_info.h>
  11 #include <mrc_cache.h>
  12 #include <device/device.h>
  13 #include <device/pci_def.h>
  14 #include <device/pci_ops.h>
  15 #include <device/dram/ddr3.h>
  16 #include <northbridge/intel/haswell/chip.h>
  17 #include <northbridge/intel/haswell/haswell.h>
  18 #include <northbridge/intel/haswell/raminit.h>
  19 #include <smbios.h>
  20 #include <spd.h>
  21 #include <security/vboot/vboot_common.h>
  22 #include <commonlib/region.h>
  23 #include <southbridge/intel/lynxpoint/me.h>
  24 #include <southbridge/intel/lynxpoint/pch.h>
  25 #include <timestamp.h>
  26 #include <types.h>
  27
  28 #include "pei_data.h"
  29
  30 #define MRC_CACHE_VERSION 1
  31
  32 static void save_mrc_data(struct pei_data *pei_data)
  33 {
  34         /* Save the MRC S3 restore data to cbmem */
  35         mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, pei_data->mrc_output,
  36                              pei_data->mrc_output_len);
  37 }
  38
  39 static void prepare_mrc_cache(struct pei_data *pei_data)
  40 {
  41         size_t mrc_size;
  42
  43         /* Preset just in case there is an error */
  44         pei_data->mrc_input = NULL;
  45         pei_data->mrc_input_len = 0;
  46
  47         pei_data->mrc_input =
  48                 mrc_cache_current_mmap_leak(MRC_TRAINING_DATA,
  49                                             MRC_CACHE_VERSION,
  50                                             &mrc_size);
  51         if (!pei_data->mrc_input)
  52                 /* Error message printed in find_current_mrc_cache */
  53                 return;
  54
  55         pei_data->mrc_input_len = mrc_size;
  56
  57         printk(BIOS_DEBUG, "%s: at %p, size %zx\n", __func__,
  58                pei_data->mrc_input, mrc_size);
  59 }
  60
  61 static const char *const ecc_decoder[] = {
  62         "inactive",
  63         "active on IO",
  64         "disabled on IO",
  65         "active",
  66 };
  67
  68 /* Print out the memory controller configuration, as per the values in its registers. */
  69 static void report_memory_config(void)
  70 {
  71         int i;
  72
  73         const u32 addr_decoder_common = mchbar_read32(MAD_CHNL);
  74
  75         printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n",
  76                (mchbar_read32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100);
  77
  78         printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n",
  79                (addr_decoder_common >> 0) & 3,
  80                (addr_decoder_common >> 2) & 3,
  81                (addr_decoder_common >> 4) & 3);
  82
  83         for (i = 0; i < NUM_CHANNELS; i++) {
  84                 const u32 ch_conf = mchbar_read32(MAD_DIMM(i));
  85
  86                 printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf);
  87                 printk(BIOS_DEBUG, "   ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]);
  88                 printk(BIOS_DEBUG, "   enhanced interleave mode %s\n",
  89                        ((ch_conf >> 22) & 1) ? "on" : "off");
  90
  91                 printk(BIOS_DEBUG, "   rank interleave %s\n",
  92                        ((ch_conf >> 21) & 1) ? "on" : "off");
  93
  94                 printk(BIOS_DEBUG, "   DIMMA %d MB width %s %s rank%s\n",
  95                        ((ch_conf >> 0) & 0xff) * 256,
  96                        ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32",
  97                        ((ch_conf >> 17) & 1) ? "dual" : "single",
  98                        ((ch_conf >> 16) & 1) ? "" : ", selected");
  99
 100                 printk(BIOS_DEBUG, "   DIMMB %d MB width %s %s rank%s\n",
 101                        ((ch_conf >> 8) & 0xff) * 256,
 102                        ((ch_conf >> 20) & 1) ? "x16" : "x8 or x32",
 103                        ((ch_conf >> 18) & 1) ? "dual" : "single",
 104                        ((ch_conf >> 16) & 1) ? ", selected" : "");
 105         }
 106 }
 107
 108 /**
 109  * Find PEI executable in coreboot filesystem and execute it.
 110  *
 111  * @param pei_data: configuration data for UEFI PEI reference code
 112  */
 113 static void sdram_initialize(struct pei_data *pei_data)
 114 {
 115         int (*entry)(struct pei_data *pei_data) __attribute__((regparm(1)));
 116
 117         printk(BIOS_DEBUG, "Starting UEFI PEI System Agent\n");
 118
 119         /*
 120          * Always pass in mrc_cache data.  The driver will determine
 121          * whether to use the data or not.
 122          */
 123         prepare_mrc_cache(pei_data);
 124
 125         /* If MRC data is not found, we cannot continue S3 resume */
 126         if (pei_data->boot_mode == 2 && !pei_data->mrc_input) {
 127                 post_code(POST_RESUME_FAILURE);
 128                 printk(BIOS_DEBUG, "Giving up in %s: No MRC data\n", __func__);
 129                 system_reset();
 130         }
 131
 132         /* Pass console handler in pei_data */
 133         pei_data->tx_byte = do_putchar;
 134
 135         /*
 136          * Locate and call UEFI System Agent binary. The binary needs to be at a fixed offset
 137          * in the flash and can therefore only reside in the COREBOOT fmap region. We don't care
 138          * about leaking the mapping.
 139          */
 140         entry = cbfs_ro_map("mrc.bin", NULL);
 141         if (entry) {
 142                 int rv = entry(pei_data);
 143
 144                 /* The mrc.bin reconfigures USB, so usbdebug needs to be reinitialized */
 145                 if (CONFIG(USBDEBUG_IN_PRE_RAM))
 146                         usbdebug_hw_init(true);
 147
 148                 if (rv) {
 149                         switch (rv) {
 150                         case -1:
 151                                 printk(BIOS_ERR, "PEI version mismatch.\n");
 152                                 break;
 153                         case -2:
 154                                 printk(BIOS_ERR, "Invalid memory frequency.\n");
 155                                 break;
 156                         default:
 157                                 printk(BIOS_ERR, "MRC returned %x.\n", rv);
 158                         }
 159                         die_with_post_code(POST_INVALID_VENDOR_BINARY,
 160                                            "Nonzero MRC return value.\n");
 161                 }
 162         } else {
 163                 die("UEFI PEI System Agent not found.\n");
 164         }
 165
 166         /* Print the MRC version after executing the UEFI PEI stage */
 167         u32 version = mchbar_read32(MRC_REVISION);
 168         printk(BIOS_DEBUG, "MRC Version %u.%u.%u Build %u\n",
 169                 (version >> 24) & 0xff, (version >> 16) & 0xff,
 170                 (version >>  8) & 0xff, (version >>  0) & 0xff);
 171
 172         /*
 173          * MRC may return zero even when raminit did not complete successfully.
 174          * Ensure the mc_init_done_ack bit is set before continuing. Otherwise,
 175          * attempting to access memory will lock up the system.
 176          */
 177         if (!(mchbar_read32(MC_INIT_STATE_G) & (1 << 5))) {
 178                 printk(BIOS_EMERG, "Memory controller did not acknowledge raminit.\n");
 179                 die("MRC raminit failed\n");
 180         }
 181
 182         report_memory_config();
 183 }
 184
 185 static uint8_t nb_get_ecc_type(const uint32_t capid0_a)
 186 {
 187         return capid0_a & CAPID_ECCDIS ? MEMORY_ARRAY_ECC_NONE : MEMORY_ARRAY_ECC_SINGLE_BIT;
 188 }
 189
 190 static uint16_t nb_slots_per_channel(const uint32_t capid0_a)
 191 {
 192         return !(capid0_a & CAPID_DDPCD) + 1;
 193 }
 194
 195 static uint16_t nb_number_of_channels(const uint32_t capid0_a)
 196 {
 197         return !(capid0_a & CAPID_PDCD) + 1;
 198 }
 199
 200 static uint32_t nb_max_chan_capacity_mib(const uint32_t capid0_a)
 201 {
 202         uint32_t ddrsz;
 203
 204         /* Values from documentation, which assume two DIMMs per channel */
 205         switch (CAPID_DDRSZ(capid0_a)) {
 206         case 1:
 207                 ddrsz = 8192;
 208                 break;
 209         case 2:
 210                 ddrsz = 2048;
 211                 break;
 212         case 3:
 213                 ddrsz = 512;
 214                 break;
 215         default:
 216                 ddrsz = 16384;
 217                 break;
 218         }
 219
 220         /* Account for the maximum number of DIMMs per channel */
 221         return (ddrsz / 2) * nb_slots_per_channel(capid0_a);
 222 }
 223
 224 static void setup_sdram_meminfo(struct pei_data *pei_data)
 225 {
 226         struct memory_info *mem_info;
 227         struct dimm_info *dimm;
 228         int ch, d_num;
 229         int dimm_cnt = 0;
 230
 231         mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(struct memory_info));
 232         if (!mem_info)
 233                 die("Failed to add memory info to CBMEM.\n");
 234
 235         memset(mem_info, 0, sizeof(struct memory_info));
 236
 237         const u32 ddr_freq_mhz = (mchbar_read32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100;
 238
 239         for (ch = 0; ch < NUM_CHANNELS; ch++) {
 240                 const u32 ch_conf = mchbar_read32(MAD_DIMM(ch));
 241                 /* DIMMs A/B */
 242                 for (d_num = 0; d_num < NUM_SLOTS; d_num++) {
 243                         const u32 dimm_size = ((ch_conf >> (d_num * 8)) & 0xff) * 256;
 244                         if (dimm_size) {
 245                                 const int index = ch * NUM_SLOTS + d_num;
 246                                 dimm = &mem_info->dimm[dimm_cnt];
 247                                 dimm->dimm_size = dimm_size;
 248                                 dimm->ddr_type = MEMORY_TYPE_DDR3;
 249                                 dimm->ddr_frequency = ddr_freq_mhz * 2; /* In MT/s */
 250                                 dimm->rank_per_dimm = 1 + ((ch_conf >> (17 + d_num)) & 1);
 251                                 dimm->channel_num = ch;
 252                                 dimm->dimm_num = d_num;
 253                                 dimm->bank_locator = ch * 2;
 254                                 memcpy(dimm->serial,
 255                                         &pei_data->spd_data[index][SPD_DIMM_SERIAL_NUM],
 256                                         SPD_DIMM_SERIAL_LEN);
 257                                 memcpy(dimm->module_part_number,
 258                                         &pei_data->spd_data[index][SPD_DIMM_PART_NUM],
 259                                         SPD_DIMM_PART_LEN);
 260                                 dimm->mod_id =
 261                                         (pei_data->spd_data[index][SPD_DIMM_MOD_ID2] << 8) |
 262                                         (pei_data->spd_data[index][SPD_DIMM_MOD_ID1] & 0xff);
 263                                 dimm->mod_type = DDR3_SPD_SODIMM;
 264                                 dimm->bus_width = MEMORY_BUS_WIDTH_64;
 265                                 dimm_cnt++;
 266                         }
 267                 }
 268         }
 269         mem_info->dimm_cnt = dimm_cnt;
 270
 271         const uint32_t capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A);
 272
 273         const uint16_t channels = nb_number_of_channels(capid0_a);
 274
 275         mem_info->ecc_type = nb_get_ecc_type(capid0_a);
 276         mem_info->max_capacity_mib = channels * nb_max_chan_capacity_mib(capid0_a);
 277         mem_info->number_of_devices = channels * nb_slots_per_channel(capid0_a);
 278 }
 279
 280 /* Copy SPD data for on-board memory */
 281 static void copy_spd(struct pei_data *pei_data, struct spd_info *spdi)
 282 {
 283         if (!CONFIG(HAVE_SPD_IN_CBFS))
 284                 return;
 285
 286         printk(BIOS_DEBUG, "SPD index %d\n", spdi->spd_index);
 287
 288         size_t spd_file_len;
 289         uint8_t *spd_file = cbfs_map("spd.bin", &spd_file_len);
 290
 291         if (!spd_file)
 292                 die("SPD data not found.");
 293
 294         if (spd_file_len < ((spdi->spd_index + 1) * SPD_LEN)) {
 295                 printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
 296                 spdi->spd_index = 0;
 297         }
 298
 299         if (spd_file_len < SPD_LEN)
 300                 die("Missing SPD data.");
 301
 302         /* MRC only uses index 0, but coreboot uses the other indices */
 303         memcpy(pei_data->spd_data[0], spd_file + (spdi->spd_index * SPD_LEN), SPD_LEN);
 304
 305         for (size_t i = 1; i < ARRAY_SIZE(spdi->addresses); i++) {
 306                 if (spdi->addresses[i] == SPD_MEMORY_DOWN)
 307                         memcpy(pei_data->spd_data[i], pei_data->spd_data[0], SPD_LEN);
 308         }
 309 }
 310
 311 /*
 312  * 0 = leave channel enabled
 313  * 1 = disable dimm 0 on channel
 314  * 2 = disable dimm 1 on channel
 315  * 3 = disable dimm 0+1 on channel
 316  */
 317 static int make_channel_disabled_mask(const struct pei_data *pd, int ch)
 318 {
 319         return (!pd->spd_addresses[ch + ch] << 0) | (!pd->spd_addresses[ch + ch + 1] << 1);
 320 }
 321
 322 static enum pei_usb2_port_location map_to_pei_usb2_location(const enum usb2_port_location loc)
 323 {
 324         static const enum pei_usb2_port_location map[] = {
 325                 [USB_PORT_SKIP]         = PEI_USB_PORT_SKIP,
 326                 [USB_PORT_BACK_PANEL]   = PEI_USB_PORT_BACK_PANEL,
 327                 [USB_PORT_FRONT_PANEL]  = PEI_USB_PORT_FRONT_PANEL,
 328                 [USB_PORT_DOCK]         = PEI_USB_PORT_DOCK,
 329                 [USB_PORT_MINI_PCIE]    = PEI_USB_PORT_MINI_PCIE,
 330                 [USB_PORT_FLEX]         = PEI_USB_PORT_FLEX,
 331                 [USB_PORT_INTERNAL]     = PEI_USB_PORT_INTERNAL,
 332         };
 333         return loc >= ARRAY_SIZE(map) ? PEI_USB_PORT_SKIP : map[loc];
 334 }
 335
 336 static uint8_t map_to_pei_oc_pin(const uint8_t oc_pin)
 337 {
 338         return oc_pin >= USB_OC_PIN_SKIP ? PEI_USB_OC_PIN_SKIP : oc_pin;
 339 }
 340
 341 void perform_raminit(const int s3resume)
 342 {
 343         const struct device *gbe = pcidev_on_root(0x19, 0);
 344
 345         const struct northbridge_intel_haswell_config *cfg = config_of_soc();
 346
 347         struct pei_data pei_data = {
 348                 .pei_version            = PEI_VERSION,
 349                 .mchbar                 = CONFIG_FIXED_MCHBAR_MMIO_BASE,
 350                 .dmibar                 = CONFIG_FIXED_DMIBAR_MMIO_BASE,
 351                 .epbar                  = CONFIG_FIXED_EPBAR_MMIO_BASE,
 352                 .pciexbar               = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
 353                 .smbusbar               = CONFIG_FIXED_SMBUS_IO_BASE,
 354                 .hpet_address           = CONFIG_HPET_ADDRESS,
 355                 .rcba                   = CONFIG_FIXED_RCBA_MMIO_BASE,
 356                 .pmbase                 = DEFAULT_PMBASE,
 357                 .gpiobase               = DEFAULT_GPIOBASE,
 358                 .temp_mmio_base         = 0xfed08000,
 359                 .system_type            = get_pch_platform_type(),
 360                 .tseg_size              = CONFIG_SMM_TSEG_SIZE,
 361                 .ec_present             = cfg->ec_present,
 362                 .gbe_enable             = gbe && gbe->enabled,
 363                 .ddr_refresh_2x         = CONFIG(ENABLE_DDR_2X_REFRESH),
 364                 .dq_pins_interleaved    = cfg->dq_pins_interleaved,
 365                 .max_ddr3_freq          = 1600,
 366                 .usb_xhci_on_resume     = cfg->usb_xhci_on_resume,
 367         };
 368
 369         for (size_t i = 0; i < ARRAY_SIZE(mainboard_usb2_ports); i++) {
 370                 /* If a port is not enabled, skip it */
 371                 if (!mainboard_usb2_ports[i].enable) {
 372                         pei_data.usb2_ports[i].over_current_pin = PEI_USB_OC_PIN_SKIP;
 373                         pei_data.usb2_ports[i].location         = PEI_USB_PORT_SKIP;
 374                         continue;
 375                 }
 376                 const enum usb2_port_location loc = mainboard_usb2_ports[i].location;
 377                 const uint8_t oc_pin = mainboard_usb2_ports[i].oc_pin;
 378                 pei_data.usb2_ports[i].length           = mainboard_usb2_ports[i].length;
 379                 pei_data.usb2_ports[i].enable           = mainboard_usb2_ports[i].enable;
 380                 pei_data.usb2_ports[i].over_current_pin = map_to_pei_oc_pin(oc_pin);
 381                 pei_data.usb2_ports[i].location         = map_to_pei_usb2_location(loc);
 382         }
 383
 384         for (size_t i = 0; i < ARRAY_SIZE(mainboard_usb3_ports); i++) {
 385                 const uint8_t oc_pin = mainboard_usb3_ports[i].oc_pin;
 386                 pei_data.usb3_ports[i].enable           = mainboard_usb3_ports[i].enable;
 387                 pei_data.usb3_ports[i].over_current_pin = map_to_pei_oc_pin(oc_pin);
 388         }
 389
 390         /* MRC has hardcoded assumptions of 2 meaning S3 wake. Normalize it here. */
 391         pei_data.boot_mode = s3resume ? 2 : 0;
 392
 393         /* Obtain the SPD addresses from mainboard code */
 394         struct spd_info spdi = {0};
 395         mb_get_spd_map(&spdi);
 396
 397         /* MRC expects left-aligned SMBus addresses, and 0xff for memory-down */
 398         for (size_t i = 0; i < ARRAY_SIZE(spdi.addresses); i++) {
 399                 const uint8_t addr = spdi.addresses[i];
 400                 pei_data.spd_addresses[i] = addr == SPD_MEMORY_DOWN ? 0xff : addr << 1;
 401         }
 402
 403         /* Calculate unimplemented DIMM slots for each channel */
 404         pei_data.dimm_channel0_disabled = make_channel_disabled_mask(&pei_data, 0);
 405         pei_data.dimm_channel1_disabled = make_channel_disabled_mask(&pei_data, 1);
 406
 407         timestamp_add_now(TS_BEFORE_INITRAM);
 408
 409         copy_spd(&pei_data, &spdi);
 410
 411         sdram_initialize(&pei_data);
 412
 413         timestamp_add_now(TS_AFTER_INITRAM);
 414
 415         post_code(0x3b);
 416
 417         intel_early_me_status();
 418
 419         int cbmem_was_initted = !cbmem_recovery(s3resume);
 420         if (s3resume && !cbmem_was_initted) {
 421                 /* Failed S3 resume, reset to come up cleanly */
 422                 printk(BIOS_CRIT, "Failed to recover CBMEM in S3 resume.\n");
 423                 system_reset();
 424         }
 425
 426         /* Save data returned from MRC on non-S3 resumes. */
 427         if (!s3resume)
 428                 save_mrc_data(&pei_data);
 429
 430         setup_sdram_meminfo(&pei_data);
 431 }