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nb/i945/gma: Store vga_disable if MAINBOARD_DO_NATIVE_VGA_INIT
[coreboot.git] / src / northbridge / intel / i945 / gma.c
blobd08b77d3e2ef756e9c1814cede8d7c756a717c1b
1 /*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2008-2009 coresystems GmbH
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <console/console.h>
17 #include <bootmode.h>
18 #include <device/mmio.h>
19 #include <delay.h>
20 #include <arch/io.h>
21 #include <device/device.h>
22 #include <device/pci.h>
23 #include <device/pci_ops.h>
24 #include <device/pci_ids.h>
25 #include <pc80/mc146818rtc.h>
26 #include <edid.h>
27 #include <drivers/intel/gma/edid.h>
28 #include <drivers/intel/gma/i915.h>
29 #include <drivers/intel/gma/opregion.h>
30 #include <string.h>
31 #include <pc80/vga.h>
32 #include <pc80/vga_io.h>
33 #include <commonlib/helpers.h>
34 #include <cbmem.h>
35 #include <southbridge/intel/i82801gx/nvs.h>
36 #include <types.h>
37
38 #include "i945.h"
39 #include "chip.h"
40
41 #define GDRST 0xc0
42 #define MSAC 0x62 /* Multi Size Aperture Control */
43
44 #define LVDS_CLOCK_A_POWERUP_ALL (3 << 8)
45 #define LVDS_CLOCK_B_POWERUP_ALL (3 << 4)
46 #define LVDS_CLOCK_BOTH_POWERUP_ALL (3 << 2)
47
48 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
49
50 #define DPLL_INTEGRATED_CRI_CLK_VLV (1 << 14)
51
52 #define PGETBL_CTL 0x2020
53 #define PGETBL_ENABLED 0x00000001
54
55 #define BASE_FREQUENCY 100000
56
57 #define DEFAULT_BLC_PWM 180
58
59 uintptr_t gma_get_gnvs_aslb(const void *gnvs)
60 {
61 const global_nvs_t *gnvs_ptr = gnvs;
62 return (uintptr_t)(gnvs_ptr ? gnvs_ptr->aslb : 0);
63 }
64
65 void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb)
66 {
67 global_nvs_t *gnvs_ptr = gnvs;
68 if (gnvs_ptr)
69 gnvs_ptr->aslb = aslb;
70 }
71
72 static int gtt_setup(u8 *mmiobase)
73 {
74 unsigned long PGETBL_save;
75 unsigned long tom; // top of memory
76
77 /*
78 * The Video BIOS places the GTT right below top of memory.
79 */
80 tom = pci_read_config8(pcidev_on_root(0, 0), TOLUD) << 24;
81 PGETBL_save = tom - 256 * KiB;
82 PGETBL_save |= PGETBL_ENABLED;
83 PGETBL_save |= 2; /* set GTT to 256kb */
84
85 write32(mmiobase + GFX_FLSH_CNTL, 0);
86
87 write32(mmiobase + PGETBL_CTL, PGETBL_save);
88
89 /* verify */
90 if (read32(mmiobase + PGETBL_CTL) & PGETBL_ENABLED) {
91 printk(BIOS_DEBUG, "gtt_setup is enabled.\n");
92 } else {
93 printk(BIOS_DEBUG, "gtt_setup failed!!!\n");
94 return 1;
95 }
96 write32(mmiobase + GFX_FLSH_CNTL, 0);
97
98 return 0;
99 }
100
101 static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf,
102 unsigned int pphysbase, unsigned int piobase,
103 u8 *mmiobase, unsigned int pgfx)
104 {
105 struct edid edid;
106 struct edid_mode *mode;
107 u8 edid_data[128];
108 unsigned long temp;
109 int hpolarity, vpolarity;
110 u32 smallest_err = 0xffffffff;
111 u32 target_frequency;
112 u32 pixel_p1 = 1;
113 u32 pixel_p2;
114 u32 pixel_n = 1;
115 u32 pixel_m1 = 1;
116 u32 pixel_m2 = 1;
117 u32 hactive, vactive, right_border, bottom_border;
118 u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch;
119 u32 i, j;
120 u32 uma_size;
121 u16 reg16;
122
123 printk(BIOS_SPEW,
124 "i915lightup: graphics %p mmio %p addrport %04x physbase %08x\n",
125 (void *)pgfx, mmiobase, piobase, pphysbase);
126
127 intel_gmbus_read_edid(mmiobase + GMBUS0, GMBUS_PORT_PANEL, 0x50,
128 edid_data, sizeof(edid_data));
129 decode_edid(edid_data, sizeof(edid_data), &edid);
130 mode = &edid.mode;
131
132 hpolarity = (mode->phsync == '-');
133 vpolarity = (mode->pvsync == '-');
134 hactive = edid.x_resolution;
135 vactive = edid.y_resolution;
136 right_border = mode->hborder;
137 bottom_border = mode->vborder;
138 vblank = mode->vbl;
139 hblank = mode->hbl;
140 vsync = mode->vspw;
141 hsync = mode->hspw;
142 hfront_porch = mode->hso;
143 vfront_porch = mode->vso;
144
145 for (i = 0; i < 2; i++)
146 for (j = 0; j < 0x100; j++)
147 /* R = j, G = j, B = j. */
148 write32(mmiobase + PALETTE(i) + 4 * j, 0x10101 * j);
149
150 write32(mmiobase + PCH_PP_CONTROL, PANEL_UNLOCK_REGS
151 | (read32(mmiobase + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK));
152
153 write32(mmiobase + MI_ARB_STATE, MI_ARB_C3_LP_WRITE_ENABLE | (1 << 27));
154 /* Clean registers. */
155 for (i = 0; i < 0x20; i += 4)
156 write32(mmiobase + RENDER_RING_BASE + i, 0);
157 for (i = 0; i < 0x20; i += 4)
158 write32(mmiobase + FENCE_REG_965_0 + i, 0);
159
160 /* Disable VGA. */
161 write32(mmiobase + VGACNTRL, VGA_DISP_DISABLE);
162
163 /* Disable pipes. */
164 write32(mmiobase + PIPECONF(0), 0);
165 write32(mmiobase + PIPECONF(1), 0);
166
167 /* Init PRB0. */
168 write32(mmiobase + HWS_PGA, 0x352d2000);
169 write32(mmiobase + PRB0_CTL, 0);
170 write32(mmiobase + PRB0_HEAD, 0);
171 write32(mmiobase + PRB0_TAIL, 0);
172 write32(mmiobase + PRB0_START, 0);
173 write32(mmiobase + PRB0_CTL, 0x0001f001);
174
175 write32(mmiobase + D_STATE, DSTATE_PLL_D3_OFF
176 | DSTATE_GFX_CLOCK_GATING | DSTATE_DOT_CLOCK_GATING);
177 write32(mmiobase + ECOSKPD, 0x00010000);
178 write32(mmiobase + HWSTAM, 0xeffe);
179 write32(mmiobase + PORT_HOTPLUG_EN, conf->gpu_hotplug);
180 write32(mmiobase + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS);
181
182 /* p2 divisor must 7 for dual channel LVDS */
183 /* and 14 for single channel LVDS */
184 pixel_p2 = mode->lvds_dual_channel ? 7 : 14;
185 target_frequency = mode->pixel_clock;
186
187 /* Find suitable divisors, m1, m2, p1, n. */
188 /* refclock * (5 * (m1 + 2) + (m1 + 2)) / (n + 2) / p1 / p2 */
189 /* should be closest to target frequency as possible */
190 u32 candn, candm1, candm2, candp1;
191 for (candm1 = 8; candm1 <= 18; candm1++) {
192 for (candm2 = 3; candm2 <= 7; candm2++) {
193 for (candn = 1; candn <= 6; candn++) {
194 for (candp1 = 1; candp1 <= 8; candp1++) {
195 u32 m = 5 * (candm1 + 2) + (candm2 + 2);
196 u32 p = candp1 * pixel_p2;
197 u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUENCY * m, candn + 2);
198 u32 dot = DIV_ROUND_CLOSEST(vco, p);
199 u32 this_err = MAX(dot, target_frequency) -
200 MIN(dot, target_frequency);
201 if ((m < 70) || (m > 120))
202 continue;
203 if (this_err < smallest_err) {
204 smallest_err = this_err;
205 pixel_n = candn;
206 pixel_m1 = candm1;
207 pixel_m2 = candm2;
208 pixel_p1 = candp1;
209 }
210 }
211 }
212 }
213 }
214
215 if (smallest_err == 0xffffffff) {
216 printk(BIOS_ERR, "Couldn't find GFX clock divisors\n");
217 return -1;
218 }
219
220 printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",
221 hactive, vactive);
222 printk(BIOS_DEBUG, "Borders %d x %d\n", right_border, bottom_border);
223 printk(BIOS_DEBUG, "Blank %d x %d\n", hblank, vblank);
224 printk(BIOS_DEBUG, "Sync %d x %d\n", hsync, vsync);
225 printk(BIOS_DEBUG, "Front porch %d x %d\n", hfront_porch, vfront_porch);
226 printk(BIOS_DEBUG, (conf->gpu_lvds_use_spread_spectrum_clock
227 ? "Spread spectrum clock\n"
228 : "DREF clock\n"));
229 printk(BIOS_DEBUG, (mode->lvds_dual_channel
230 ? "Dual channel\n"
231 : "Single channel\n"));
232 printk(BIOS_DEBUG, "Polarities %d, %d\n",
233 hpolarity, vpolarity);
234 printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n",
235 pixel_n, pixel_m1, pixel_m2, pixel_p1);
236 printk(BIOS_DEBUG, "Pixel clock %d kHz\n",
237 BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) /
238 (pixel_n + 2) / (pixel_p1 * pixel_p2));
239
240 printk(BIOS_INFO, "VGA mode: %s\n", CONFIG(LINEAR_FRAMEBUFFER) ?
241 "Linear framebuffer" : "text");
242 if (CONFIG(LINEAR_FRAMEBUFFER)) {
243 /* Disable panel fitter (we're in native resolution). */
244 write32(mmiobase + PF_CTL(0), 0);
245 write32(mmiobase + PF_WIN_SZ(0), 0);
246 write32(mmiobase + PF_WIN_POS(0), 0);
247 write32(mmiobase + PFIT_PGM_RATIOS, 0);
248 write32(mmiobase + PFIT_CONTROL, 0);
249 } else {
250 write32(mmiobase + PF_WIN_SZ(0), vactive | (hactive << 16));
251 write32(mmiobase + PF_WIN_POS(0), 0);
252 write32(mmiobase + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3);
253 write32(mmiobase + PFIT_CONTROL, PFIT_ENABLE
254 | (1 << PFIT_PIPE_SHIFT) | HORIZ_AUTO_SCALE
255 | VERT_AUTO_SCALE);
256 }
257
258 mdelay(1);
259
260 write32(mmiobase + DSPCNTR(0), DISPPLANE_BGRX888
261 | DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE);
262
263 mdelay(1);
264 write32(mmiobase + PP_CONTROL, PANEL_UNLOCK_REGS
265 | (read32(mmiobase + PP_CONTROL) & ~PANEL_UNLOCK_MASK));
266 write32(mmiobase + FP0(1),
267 (pixel_n << 16)
268 | (pixel_m1 << 8) | pixel_m2);
269 write32(mmiobase + DPLL(1),
270 DPLL_VGA_MODE_DIS |
271 DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
272 | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
273 : DPLLB_LVDS_P2_CLOCK_DIV_14)
274 | (conf->gpu_lvds_use_spread_spectrum_clock
275 ? DPLL_INTEGRATED_CLOCK_VLV | DPLL_INTEGRATED_CRI_CLK_VLV
276 : 0)
277 | (0x10000 << (pixel_p1 - 1)));
278 mdelay(1);
279 write32(mmiobase + DPLL(1),
280 DPLL_VGA_MODE_DIS |
281 DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
282 | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
283 : DPLLB_LVDS_P2_CLOCK_DIV_14)
284 | ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13)
285 | (0x10000 << (pixel_p1 - 1)));
286 mdelay(1);
287 write32(mmiobase + HTOTAL(1),
288 ((hactive + right_border + hblank - 1) << 16)
289 | (hactive - 1));
290 write32(mmiobase + HBLANK(1),
291 ((hactive + right_border + hblank - 1) << 16)
292 | (hactive + right_border - 1));
293 write32(mmiobase + HSYNC(1),
294 ((hactive + right_border + hfront_porch + hsync - 1) << 16)
295 | (hactive + right_border + hfront_porch - 1));
296
297 write32(mmiobase + VTOTAL(1), ((vactive + bottom_border + vblank - 1) << 16)
298 | (vactive - 1));
299 write32(mmiobase + VBLANK(1), ((vactive + bottom_border + vblank - 1) << 16)
300 | (vactive + bottom_border - 1));
301 write32(mmiobase + VSYNC(1),
302 ((vactive + bottom_border + vfront_porch + vsync - 1) << 16)
303 | (vactive + bottom_border + vfront_porch - 1));
304
305 if (CONFIG(LINEAR_FRAMEBUFFER)) {
306 write32(mmiobase + PIPESRC(1), ((hactive - 1) << 16)
307 | (vactive - 1));
308 } else {
309 write32(mmiobase + PIPESRC(1), (639 << 16) | 399);
310 }
311
312 mdelay(1);
313
314 write32(mmiobase + DSPSIZE(0), (hactive - 1) | ((vactive - 1) << 16));
315 write32(mmiobase + DSPPOS(0), 0);
316
317 edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63;
318 write32(mmiobase + DSPADDR(0), 0);
319 write32(mmiobase + DSPSURF(0), 0);
320 write32(mmiobase + DSPSTRIDE(0), edid.bytes_per_line);
321 write32(mmiobase + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888
322 | DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE);
323 mdelay(1);
324
325 write32(mmiobase + PIPECONF(1), PIPECONF_ENABLE);
326 write32(mmiobase + LVDS, LVDS_ON
327 | (hpolarity << 20) | (vpolarity << 21)
328 | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
329 | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
330 | LVDS_CLOCK_A_POWERUP_ALL
331 | LVDS_PIPE(1));
332
333 write32(mmiobase + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
334 write32(mmiobase + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET);
335 mdelay(1);
336 write32(mmiobase + PP_CONTROL, PANEL_UNLOCK_REGS
337 | PANEL_POWER_ON | PANEL_POWER_RESET);
338
339 printk(BIOS_DEBUG, "waiting for panel powerup\n");
340 while (1) {
341 u32 reg32;
342 reg32 = read32(mmiobase + PP_STATUS);
343 if ((reg32 & PP_SEQUENCE_MASK) == PP_SEQUENCE_NONE)
344 break;
345 }
346 printk(BIOS_DEBUG, "panel powered up\n");
347
348 write32(mmiobase + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET);
349
350 /* Clear interrupts. */
351 write32(mmiobase + DEIIR, 0xffffffff);
352 write32(mmiobase + SDEIIR, 0xffffffff);
353 write32(mmiobase + IIR, 0xffffffff);
354 write32(mmiobase + IMR, 0xffffffff);
355 write32(mmiobase + EIR, 0xffffffff);
356
357 if (gtt_setup(mmiobase)) {
358 printk(BIOS_ERR, "ERROR: GTT Setup Failed!!!\n");
359 return 0;
360 }
361
362 /* Setup GTT. */
363
364 reg16 = pci_read_config16(pcidev_on_root(0, 0), GGC);
365 uma_size = 0;
366 if (!(reg16 & 2)) {
367 uma_size = decode_igd_memory_size((reg16 >> 4) & 7);
368 printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10);
369 }
370
371 for (i = 0; i < (uma_size - 256) / 4; i++) {
372 outl((i << 2) | 1, piobase);
373 outl(pphysbase + (i << 12) + 1, piobase + 4);
374 }
375
376 temp = read32(mmiobase + PGETBL_CTL);
377 printk(BIOS_INFO, "GTT PGETBL_CTL register: 0x%lx\n", temp);
378
379 if (temp & 1)
380 printk(BIOS_INFO, "GTT Enabled\n");
381 else
382 printk(BIOS_ERR, "ERROR: GTT is still Disabled!!!\n");
383
384 if (CONFIG(LINEAR_FRAMEBUFFER)) {
385 printk(BIOS_SPEW, "memset %p to 0x00 for %d bytes\n",
386 (void *)pgfx, hactive * vactive * 4);
387 memset((void *)pgfx, 0x00, hactive * vactive * 4);
388
389 set_vbe_mode_info_valid(&edid, pgfx);
390 } else {
391 vga_misc_write(0x67);
392
393 write32(mmiobase + DSPCNTR(0), DISPPLANE_SEL_PIPE_B);
394 write32(mmiobase + VGACNTRL, 0x02c4008e
395 | VGA_PIPE_B_SELECT);
396
397 vga_textmode_init();
398 }
399 return 0;
400 }
401
402 static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf,
403 unsigned int pphysbase, unsigned int piobase,
404 u8 *mmiobase, unsigned int pgfx)
405 {
406 int i;
407 u32 hactive, vactive;
408 u16 reg16;
409 u32 uma_size;
410
411 printk(BIOS_SPEW, "mmiobase %x addrport %x physbase %x\n",
412 (u32)mmiobase, piobase, pphysbase);
413
414 gtt_setup(mmiobase);
415
416 /* Disable VGA. */
417 write32(mmiobase + VGACNTRL, VGA_DISP_DISABLE);
418
419 /* Disable pipes. */
420 write32(mmiobase + PIPECONF(0), 0);
421 write32(mmiobase + PIPECONF(1), 0);
422
423 write32(mmiobase + INSTPM, 0x800);
424
425 vga_gr_write(0x18, 0);
426
427 write32(mmiobase + VGA0, 0x200074);
428 write32(mmiobase + VGA1, 0x200074);
429
430 write32(mmiobase + DSPFW3, 0x7f3f00c1 & ~PINEVIEW_SELF_REFRESH_EN);
431 write32(mmiobase + DSPCLK_GATE_D, 0);
432 write32(mmiobase + FW_BLC, 0x03060106);
433 write32(mmiobase + FW_BLC2, 0x00000306);
434
435 write32(mmiobase + ADPA, ADPA_DAC_ENABLE
436 | ADPA_PIPE_A_SELECT
437 | ADPA_USE_VGA_HVPOLARITY
438 | ADPA_VSYNC_CNTL_ENABLE
439 | ADPA_HSYNC_CNTL_ENABLE
440 | ADPA_DPMS_ON
441 );
442
443 write32(mmiobase + 0x7041c, 0x0);
444
445 write32(mmiobase + DPLL_MD(0), 0x3);
446 write32(mmiobase + DPLL_MD(1), 0x3);
447 write32(mmiobase + DSPCNTR(1), 0x1000000);
448 write32(mmiobase + PIPESRC(1), 0x027f01df);
449
450 vga_misc_write(0x67);
451 const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
452 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00,
453 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3,
454 0xff
455 };
456 vga_cr_write(0x11, 0);
457
458 for (i = 0; i <= 0x18; i++)
459 vga_cr_write(i, cr[i]);
460
461 // Disable screen memory to prevent garbage from appearing.
462 vga_sr_write(1, vga_sr_read(1) | 0x20);
463 hactive = 640;
464 vactive = 400;
465
466 mdelay(1);
467 write32(mmiobase + DPLL(0),
468 DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL
469 | DPLL_VGA_MODE_DIS
470 | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
471 | 0x400601
472 );
473 mdelay(1);
474 write32(mmiobase + DPLL(0),
475 DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL
476 | DPLL_VGA_MODE_DIS
477 | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
478 | 0x400601
479 );
480
481 write32(mmiobase + ADPA, ADPA_DAC_ENABLE
482 | ADPA_PIPE_A_SELECT
483 | ADPA_USE_VGA_HVPOLARITY
484 | ADPA_VSYNC_CNTL_ENABLE
485 | ADPA_HSYNC_CNTL_ENABLE
486 | ADPA_DPMS_ON
487 );
488
489 write32(mmiobase + HTOTAL(0),
490 ((hactive - 1) << 16)
491 | (hactive - 1));
492 write32(mmiobase + HBLANK(0),
493 ((hactive - 1) << 16)
494 | (hactive - 1));
495 write32(mmiobase + HSYNC(0),
496 ((hactive - 1) << 16)
497 | (hactive - 1));
498
499 write32(mmiobase + VTOTAL(0), ((vactive - 1) << 16)
500 | (vactive - 1));
501 write32(mmiobase + VBLANK(0), ((vactive - 1) << 16)
502 | (vactive - 1));
503 write32(mmiobase + VSYNC(0),
504 ((vactive - 1) << 16)
505 | (vactive - 1));
506
507 write32(mmiobase + PF_WIN_POS(0), 0);
508
509 write32(mmiobase + PIPESRC(0), (639 << 16) | 399);
510 write32(mmiobase + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3);
511 write32(mmiobase + PF_WIN_SZ(0), vactive | (hactive << 16));
512 write32(mmiobase + PFIT_CONTROL, 0x0);
513
514 mdelay(1);
515
516 write32(mmiobase + FDI_RX_CTL(0), 0x00002040);
517 mdelay(1);
518 write32(mmiobase + FDI_RX_CTL(0), 0x80002050);
519 write32(mmiobase + FDI_TX_CTL(0), 0x00044000);
520 mdelay(1);
521 write32(mmiobase + FDI_TX_CTL(0), 0x80044000);
522 write32(mmiobase + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
523
524 write32(mmiobase + VGACNTRL, 0x0);
525 write32(mmiobase + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
526 mdelay(1);
527
528 write32(mmiobase + ADPA, ADPA_DAC_ENABLE
529 | ADPA_PIPE_A_SELECT
530 | ADPA_USE_VGA_HVPOLARITY
531 | ADPA_VSYNC_CNTL_ENABLE
532 | ADPA_HSYNC_CNTL_ENABLE
533 | ADPA_DPMS_ON
534 );
535
536 write32(mmiobase + DSPFW3, 0x7f3f00c1);
537 write32(mmiobase + MI_MODE, 0x200 | VS_TIMER_DISPATCH);
538 write32(mmiobase + CACHE_MODE_0, (0x6820 | (1 << 9)) & ~(1 << 5));
539 write32(mmiobase + CACHE_MODE_1, 0x380 & ~(1 << 9));
540
541 /* Set up GTT. */
542
543 reg16 = pci_read_config16(pcidev_on_root(0, 0), GGC);
544 uma_size = 0;
545 if (!(reg16 & 2)) {
546 uma_size = decode_igd_memory_size((reg16 >> 4) & 7);
547 printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10);
548 }
549
550 for (i = 0; i < (uma_size - 256) / 4; i++) {
551 outl((i << 2) | 1, piobase);
552 outl(pphysbase + (i << 12) + 1, piobase + 4);
553 }
554
555 /* Clear interrupts. */
556 write32(mmiobase + DEIIR, 0xffffffff);
557 write32(mmiobase + SDEIIR, 0xffffffff);
558 write32(mmiobase + IIR, 0xffffffff);
559 write32(mmiobase + IMR, 0xffffffff);
560 write32(mmiobase + EIR, 0xffffffff);
561
562 vga_textmode_init();
563
564 /* Enable screen memory. */
565 vga_sr_write(1, vga_sr_read(1) & ~0x20);
566
567 return 0;
568
569 }
570
571 /* compare the header of the vga edid header */
572 /* if vga is not connected it should have a correct header */
573 static int probe_edid(u8 *mmiobase, u8 slave)
574 {
575 int i;
576 u8 vga_edid[128];
577 u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00};
578 intel_gmbus_read_edid(mmiobase + GMBUS0, slave, 0x50, vga_edid, 128);
579 intel_gmbus_stop(mmiobase + GMBUS0);
580 for (i = 0; i < 8; i++) {
581 if (vga_edid[i] != header[i]) {
582 printk(BIOS_DEBUG, "No display connected on slave %d\n",
583 slave);
584 return 0;
585 }
586 }
587 printk(BIOS_SPEW, "Found a display on slave %d\n", slave);
588 return 1;
589 }
590
591 static u32 get_cdclk(struct device *const dev)
592 {
593 u16 gcfgc = pci_read_config16(dev, GCFGC);
594
595 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
596 return 133333333;
597
598 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
599 case GC_DISPLAY_CLOCK_333_320_MHZ:
600 return 320000000;
601 default:
602 case GC_DISPLAY_CLOCK_190_200_MHZ:
603 return 200000000;
604 }
605 }
606
607 static u32 freq_to_blc_pwm_ctl(struct device *const dev, u16 pwm_freq)
608 {
609 u32 blc_mod;
610
611 /* Set duty cycle to 100% due to use of legacy backlight control */
612 blc_mod = get_cdclk(dev) / (32 * pwm_freq);
613 return BLM_LEGACY_MODE | ((blc_mod / 2) << 17) | ((blc_mod / 2) << 1);
614 }
615
616
617 static void panel_setup(u8 *mmiobase, struct device *const dev)
618 {
619 const struct northbridge_intel_i945_config *const conf = dev->chip_info;
620
621 u32 reg32;
622
623 /* Set up Panel Power On Delays */
624 reg32 = (conf->gpu_panel_power_up_delay & 0x1fff) << 16;
625 reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff);
626 write32(mmiobase + PP_ON_DELAYS, reg32);
627
628 /* Set up Panel Power Off Delays */
629 reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16;
630 reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff);
631 write32(mmiobase + PP_OFF_DELAYS, reg32);
632
633 /* Set up Panel Power Cycle Delay */
634 reg32 = (get_cdclk(dev) / 20000 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
635 reg32 |= conf->gpu_panel_power_cycle_delay & 0x1f;
636 write32(mmiobase + PP_DIVISOR, reg32);
637
638 /* Backlight init. */
639 if (conf->pwm_freq)
640 write32(mmiobase + BLC_PWM_CTL, freq_to_blc_pwm_ctl(dev,
641 conf->pwm_freq));
642 else
643 write32(mmiobase + BLC_PWM_CTL, freq_to_blc_pwm_ctl(dev,
644 DEFAULT_BLC_PWM));
645 }
646
647 static void gma_ngi(struct device *const dev)
648 {
649 /* This should probably run before post VBIOS init. */
650 printk(BIOS_INFO, "Initializing VGA without OPROM.\n");
651 void *mmiobase;
652 u32 iobase, graphics_base;
653 struct northbridge_intel_i945_config *conf = dev->chip_info;
654
655 iobase = dev->resource_list[1].base;
656 mmiobase = (void *)(uintptr_t)dev->resource_list[0].base;
657 graphics_base = dev->resource_list[2].base;
658
659 printk(BIOS_SPEW, "GMADR = 0x%08x GTTADR = 0x%08x\n",
660 pci_read_config32(dev, GMADR), pci_read_config32(dev, GTTADR));
661
662 int err;
663
664 if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM))
665 panel_setup(mmiobase, dev);
666
667 /* probe if VGA is connected and always run */
668 /* VGA init if no LVDS is connected */
669 if (!probe_edid(mmiobase, GMBUS_PORT_PANEL) ||
670 probe_edid(mmiobase, GMBUS_PORT_VGADDC))
671 err = intel_gma_init_vga(conf,
672 pci_read_config32(dev, 0x5c) & ~0xf,
673 iobase, mmiobase, graphics_base);
674 else
675 err = intel_gma_init_lvds(conf,
676 pci_read_config32(dev, 0x5c) & ~0xf,
677 iobase, mmiobase, graphics_base);
678 if (err == 0)
679 gfx_set_init_done(1);
680 /* Linux relies on VBT for panel info. */
681 if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) {
682 generate_fake_intel_oprom(&conf->gfx, dev, "$VBT CALISTOGA");
683 }
684 if (CONFIG(NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) {
685 generate_fake_intel_oprom(&conf->gfx, dev, "$VBT LAKEPORT-G");
686 }
687 }
688
689 static void gma_func0_init(struct device *dev)
690 {
691 u32 reg32;
692
693 /* Unconditionally reset graphics */
694 pci_write_config8(dev, GDRST, 1);
695 udelay(50);
696 pci_write_config8(dev, GDRST, 0);
697 /* wait for device to finish */
698 while (pci_read_config8(dev, GDRST) & 1)
699 ;
700
701 /* IGD needs to be Bus Master */
702 reg32 = pci_read_config32(dev, PCI_COMMAND);
703 pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER
704 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
705
706 if (CONFIG(MAINBOARD_DO_NATIVE_VGA_INIT)) {
707 int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1;
708 if (acpi_is_wakeup_s3()) {
709 printk(BIOS_INFO,
710 "Skipping native VGA initialization when resuming from ACPI S3.\n");
711 } else {
712 if (vga_disable) {
713 printk(BIOS_INFO,
714 "IGD is not decoding legacy VGA MEM and IO: skipping NATIVE graphic init\n");
715 } else {
716 gma_ngi(dev);
717 }
718 }
719 } else {
720 /* PCI Init, will run VBIOS */
721 pci_dev_init(dev);
722 }
723
724 intel_gma_restore_opregion();
725 }
726
727 /* This doesn't reclaim stolen UMA memory, but IGD could still
728 be re-enabled later. */
729 static void gma_func0_disable(struct device *dev)
730 {
731 struct device *dev_host = pcidev_on_root(0x0, 0);
732
733 pci_write_config16(dev, GCFC, 0xa00);
734 pci_write_config16(dev_host, GGC, (1 << 1));
735
736 unsigned int reg32 = pci_read_config32(dev_host, DEVEN);
737 reg32 &= ~(DEVEN_D2F0 | DEVEN_D2F1);
738 pci_write_config32(dev_host, DEVEN, reg32);
739
740 dev->enabled = 0;
741 }
742
743 static void gma_func1_init(struct device *dev)
744 {
745 u32 reg32;
746 u8 val;
747
748 /* IGD needs to be Bus Master, also enable IO access */
749 reg32 = pci_read_config32(dev, PCI_COMMAND);
750 pci_write_config32(dev, PCI_COMMAND, reg32 |
751 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
752
753 if (get_option(&val, "tft_brightness") == CB_SUCCESS)
754 pci_write_config8(dev, 0xf4, val);
755 else
756 pci_write_config8(dev, 0xf4, 0xff);
757 }
758
759 const struct i915_gpu_controller_info *
760 intel_gma_get_controller_info(void)
761 {
762 struct device *dev = pcidev_on_root(0x2, 0);
763 if (!dev)
764 return NULL;
765 struct northbridge_intel_i945_config *chip = dev->chip_info;
766 if (!chip)
767 return NULL;
768 return &chip->gfx;
769 }
770
771 static void gma_ssdt(struct device *device)
772 {
773 const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
774 if (!gfx)
775 return;
776
777 drivers_intel_gma_displays_ssdt_generate(gfx);
778 }
779
780 static void gma_func0_read_resources(struct device *dev)
781 {
782 u8 reg8;
783
784 /* Set Untrusted Aperture Size to 256mb */
785 reg8 = pci_read_config8(dev, MSAC);
786 reg8 &= ~0x3;
787 reg8 |= 0x2;
788 pci_write_config8(dev, MSAC, reg8);
789
790 pci_dev_read_resources(dev);
791 }
792
793 static unsigned long
794 gma_write_acpi_tables(struct device *const dev,
795 unsigned long current,
796 struct acpi_rsdp *const rsdp)
797 {
798 igd_opregion_t *opregion = (igd_opregion_t *)current;
799 global_nvs_t *gnvs;
800
801 if (intel_gma_init_igd_opregion(opregion) != CB_SUCCESS)
802 return current;
803
804 current += sizeof(igd_opregion_t);
805
806 /* GNVS has been already set up */
807 gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
808 if (gnvs) {
809 /* IGD OpRegion Base Address */
810 gma_set_gnvs_aslb(gnvs, (uintptr_t)opregion);
811 } else {
812 printk(BIOS_ERR, "Error: GNVS table not found.\n");
813 }
814
815 current = acpi_align_current(current);
816 return current;
817 }
818
819 static const char *gma_acpi_name(const struct device *dev)
820 {
821 return "GFX0";
822 }
823
824 static struct pci_operations gma_pci_ops = {
825 .set_subsystem = pci_dev_set_subsystem,
826 };
827
828 static struct device_operations gma_func0_ops = {
829 .read_resources = gma_func0_read_resources,
830 .set_resources = pci_dev_set_resources,
831 .enable_resources = pci_dev_enable_resources,
832 .init = gma_func0_init,
833 .acpi_fill_ssdt_generator = gma_ssdt,
834 .scan_bus = 0,
835 .enable = 0,
836 .disable = gma_func0_disable,
837 .ops_pci = &gma_pci_ops,
838 .acpi_name = gma_acpi_name,
839 .write_acpi_tables = gma_write_acpi_tables,
840 };
841
842
843 static struct device_operations gma_func1_ops = {
844 .read_resources = pci_dev_read_resources,
845 .set_resources = pci_dev_set_resources,
846 .enable_resources = pci_dev_enable_resources,
847 .init = gma_func1_init,
848 .scan_bus = 0,
849 .enable = 0,
850 .ops_pci = &gma_pci_ops,
851 };
852
853 static const unsigned short i945_gma_func0_ids[] = {
854 0x2772, /* 82945G/GZ Integrated Graphics Controller */
855 0x27a2, /* Mobile 945GM/GMS Express Integrated Graphics Controller*/
856 0x27ae, /* Mobile 945GSE Express Integrated Graphics Controller */
857 0
858 };
859
860 static const unsigned short i945_gma_func1_ids[] = {
861 0x2776, /* Desktop 82945G/GZ/GC */
862 0x27a6, /* Mobile 945GM/GMS/GME Express Integrated Graphics Controller */
863 0
864 };
865
866 static const struct pci_driver i945_gma_func0_driver __pci_driver = {
867 .ops = &gma_func0_ops,
868 .vendor = PCI_VENDOR_ID_INTEL,
869 .devices = i945_gma_func0_ids,
870 };
871
872 static const struct pci_driver i945_gma_func1_driver __pci_driver = {
873 .ops = &gma_func1_ops,
874 .vendor = PCI_VENDOR_ID_INTEL,
875 .devices = i945_gma_func1_ids,
876 };
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