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soc/intel/alderlake: Make use of `cpu/intel/cpu_ids.h'
[coreboot.git] / src / soc / intel / alderlake / fsp_params.c
blob489935d0589436255a06fc75ba97fd787ef87e51
1 /* SPDX-License-Identifier: GPL-2.0-only */
2
3 #include <assert.h>
4 #include <cbfs.h>
5 #include <console/console.h>
6 #include <device/device.h>
7 #include <device/pci.h>
8 #include <fsp/api.h>
9 #include <fsp/ppi/mp_service_ppi.h>
10 #include <fsp/util.h>
11 #include <intelblocks/irq.h>
12 #include <intelblocks/lpss.h>
13 #include <intelblocks/xdci.h>
14 #include <intelpch/lockdown.h>
15 #include <intelblocks/tcss.h>
16 #include <soc/gpio_soc_defs.h>
17 #include <soc/intel/common/vbt.h>
18 #include <soc/pci_devs.h>
19 #include <soc/pcie.h>
20 #include <soc/ramstage.h>
21 #include <soc/soc_chip.h>
22 #include <stdlib.h>
23 #include <string.h>
24
25 /* THC assignment definition */
26 #define THC_NONE 0
27 #define THC_0 1
28 #define THC_1 2
29
30 /* SATA DEVSLP idle timeout default values */
31 #define DEF_DMVAL 15
32 #define DEF_DITOVAL 625
33
34 /*
35 * ME End of Post configuration
36 * 0 - Disable EOP.
37 * 1 - Send in PEI (Applicable for FSP in API mode)
38 * 2 - Send in DXE (Not applicable for FSP in API mode)
39 */
40 enum fsp_end_of_post {
41 EOP_DISABLE = 0,
42 EOP_PEI = 1,
43 EOP_DXE = 2,
44 };
45
46 static const struct slot_irq_constraints irq_constraints[] = {
47 {
48 .slot = SA_DEV_SLOT_IGD,
49 .fns = {
50 /* INTERRUPT_PIN is RO/0x01 */
51 FIXED_INT_ANY_PIRQ(SA_DEVFN_IGD, PCI_INT_A),
52 },
53 },
54 {
55 .slot = SA_DEV_SLOT_DPTF,
56 .fns = {
57 ANY_PIRQ(SA_DEVFN_DPTF),
58 },
59 },
60 {
61 .slot = SA_DEV_SLOT_IPU,
62 .fns = {
63 /* INTERRUPT_PIN is RO/0x01, and INTERRUPT_LINE is RW,
64 but S0ix fails when not set to 16 (b/193434192) */
65 FIXED_INT_PIRQ(SA_DEVFN_IPU, PCI_INT_A, PIRQ_A),
66 },
67 },
68 {
69 .slot = SA_DEV_SLOT_CPU_6,
70 .fns = {
71 FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE6_0, PCI_INT_A, PIRQ_A),
72 FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE6_2, PCI_INT_C, PIRQ_C),
73 },
74 },
75 {
76 .slot = SA_DEV_SLOT_TBT,
77 .fns = {
78 ANY_PIRQ(SA_DEVFN_TBT0),
79 ANY_PIRQ(SA_DEVFN_TBT1),
80 ANY_PIRQ(SA_DEVFN_TBT2),
81 ANY_PIRQ(SA_DEVFN_TBT3),
82 },
83 },
84 {
85 .slot = SA_DEV_SLOT_GNA,
86 .fns = {
87 /* INTERRUPT_PIN is RO/0x01 */
88 FIXED_INT_ANY_PIRQ(SA_DEVFN_GNA, PCI_INT_A),
89 },
90 },
91 {
92 .slot = SA_DEV_SLOT_TCSS,
93 .fns = {
94 ANY_PIRQ(SA_DEVFN_TCSS_XHCI),
95 ANY_PIRQ(SA_DEVFN_TCSS_XDCI),
96 },
97 },
98 {
99 .slot = PCH_DEV_SLOT_SIO0,
100 .fns = {
101 DIRECT_IRQ(PCH_DEVFN_I2C6),
102 DIRECT_IRQ(PCH_DEVFN_I2C7),
103 ANY_PIRQ(PCH_DEVFN_THC0),
104 ANY_PIRQ(PCH_DEVFN_THC1),
105 },
106 },
107 {
108 .slot = PCH_DEV_SLOT_SIO6,
109 .fns = {
110 DIRECT_IRQ(PCH_DEVFN_UART3),
111 DIRECT_IRQ(PCH_DEVFN_UART4),
112 DIRECT_IRQ(PCH_DEVFN_UART5),
113 DIRECT_IRQ(PCH_DEVFN_UART6),
114 },
115 },
116 {
117 .slot = PCH_DEV_SLOT_ISH,
118 .fns = {
119 DIRECT_IRQ(PCH_DEVFN_ISH),
120 DIRECT_IRQ(PCH_DEVFN_GSPI2),
121 ANY_PIRQ(PCH_DEVFN_UFS),
122 },
123 },
124 {
125 .slot = PCH_DEV_SLOT_SIO2,
126 .fns = {
127 DIRECT_IRQ(PCH_DEVFN_GSPI3),
128 DIRECT_IRQ(PCH_DEVFN_GSPI4),
129 DIRECT_IRQ(PCH_DEVFN_GSPI5),
130 DIRECT_IRQ(PCH_DEVFN_GSPI6),
131 },
132 },
133 {
134 .slot = PCH_DEV_SLOT_XHCI,
135 .fns = {
136 ANY_PIRQ(PCH_DEVFN_XHCI),
137 DIRECT_IRQ(PCH_DEVFN_USBOTG),
138 ANY_PIRQ(PCH_DEVFN_CNVI_WIFI),
139 },
140 },
141 {
142 .slot = PCH_DEV_SLOT_SIO3,
143 .fns = {
144 DIRECT_IRQ(PCH_DEVFN_I2C0),
145 DIRECT_IRQ(PCH_DEVFN_I2C1),
146 DIRECT_IRQ(PCH_DEVFN_I2C2),
147 DIRECT_IRQ(PCH_DEVFN_I2C3),
148 },
149 },
150 {
151 .slot = PCH_DEV_SLOT_CSE,
152 .fns = {
153 ANY_PIRQ(PCH_DEVFN_CSE),
154 ANY_PIRQ(PCH_DEVFN_CSE_2),
155 ANY_PIRQ(PCH_DEVFN_CSE_IDER),
156 ANY_PIRQ(PCH_DEVFN_CSE_KT),
157 ANY_PIRQ(PCH_DEVFN_CSE_3),
158 ANY_PIRQ(PCH_DEVFN_CSE_4),
159 },
160 },
161 {
162 .slot = PCH_DEV_SLOT_SATA,
163 .fns = {
164 ANY_PIRQ(PCH_DEVFN_SATA),
165 },
166 },
167 {
168 .slot = PCH_DEV_SLOT_SIO4,
169 .fns = {
170 DIRECT_IRQ(PCH_DEVFN_I2C4),
171 DIRECT_IRQ(PCH_DEVFN_I2C5),
172 DIRECT_IRQ(PCH_DEVFN_UART2),
173 },
174 },
175 {
176 .slot = PCH_DEV_SLOT_PCIE,
177 .fns = {
178 FIXED_INT_PIRQ(PCH_DEVFN_PCIE1, PCI_INT_A, PIRQ_A),
179 FIXED_INT_PIRQ(PCH_DEVFN_PCIE2, PCI_INT_B, PIRQ_B),
180 FIXED_INT_PIRQ(PCH_DEVFN_PCIE3, PCI_INT_C, PIRQ_C),
181 FIXED_INT_PIRQ(PCH_DEVFN_PCIE4, PCI_INT_D, PIRQ_D),
182 FIXED_INT_PIRQ(PCH_DEVFN_PCIE5, PCI_INT_A, PIRQ_A),
183 FIXED_INT_PIRQ(PCH_DEVFN_PCIE6, PCI_INT_B, PIRQ_B),
184 FIXED_INT_PIRQ(PCH_DEVFN_PCIE7, PCI_INT_C, PIRQ_C),
185 FIXED_INT_PIRQ(PCH_DEVFN_PCIE8, PCI_INT_D, PIRQ_D),
186 },
187 },
188 {
189 .slot = PCH_DEV_SLOT_PCIE_1,
190 .fns = {
191 FIXED_INT_PIRQ(PCH_DEVFN_PCIE9, PCI_INT_A, PIRQ_A),
192 FIXED_INT_PIRQ(PCH_DEVFN_PCIE10, PCI_INT_B, PIRQ_B),
193 FIXED_INT_PIRQ(PCH_DEVFN_PCIE11, PCI_INT_C, PIRQ_C),
194 FIXED_INT_PIRQ(PCH_DEVFN_PCIE12, PCI_INT_D, PIRQ_D),
195 },
196 },
197 {
198 .slot = PCH_DEV_SLOT_SIO5,
199 .fns = {
200 /* UART0 shares an interrupt line with TSN0, so must use
201 a PIRQ */
202 FIXED_INT_ANY_PIRQ(PCH_DEVFN_UART0, PCI_INT_A),
203 /* UART1 shares an interrupt line with TSN1, so must use
204 a PIRQ */
205 FIXED_INT_ANY_PIRQ(PCH_DEVFN_UART1, PCI_INT_B),
206 DIRECT_IRQ(PCH_DEVFN_GSPI0),
207 DIRECT_IRQ(PCH_DEVFN_GSPI1),
208 },
209 },
210 {
211 .slot = PCH_DEV_SLOT_ESPI,
212 .fns = {
213 ANY_PIRQ(PCH_DEVFN_HDA),
214 ANY_PIRQ(PCH_DEVFN_SMBUS),
215 ANY_PIRQ(PCH_DEVFN_GBE),
216 /* INTERRUPT_PIN is RO/0x01 */
217 FIXED_INT_ANY_PIRQ(PCH_DEVFN_TRACEHUB, PCI_INT_A),
218 },
219 },
220 };
221
222 static const SI_PCH_DEVICE_INTERRUPT_CONFIG *pci_irq_to_fsp(size_t *out_count)
223 {
224 const struct pci_irq_entry *entry = get_cached_pci_irqs();
225 SI_PCH_DEVICE_INTERRUPT_CONFIG *config;
226 size_t pch_total = 0;
227 size_t cfg_count = 0;
228
229 if (!entry)
230 return NULL;
231
232 /* Count PCH devices */
233 while (entry) {
234 if (PCI_SLOT(entry->devfn) >= MIN_PCH_SLOT)
235 ++pch_total;
236 entry = entry->next;
237 }
238
239 /* Convert PCH device entries to FSP format */
240 config = calloc(pch_total, sizeof(*config));
241 entry = get_cached_pci_irqs();
242 while (entry) {
243 if (PCI_SLOT(entry->devfn) < MIN_PCH_SLOT) {
244 entry = entry->next;
245 continue;
246 }
247
248 config[cfg_count].Device = PCI_SLOT(entry->devfn);
249 config[cfg_count].Function = PCI_FUNC(entry->devfn);
250 config[cfg_count].IntX = (SI_PCH_INT_PIN)entry->pin;
251 config[cfg_count].Irq = entry->irq;
252 ++cfg_count;
253
254 entry = entry->next;
255 }
256
257 *out_count = cfg_count;
258
259 return config;
260 }
261
262 /*
263 * Chip config parameter PcieRpL1Substates uses (UPD value + 1)
264 * because UPD value of 0 for PcieRpL1Substates means disabled for FSP.
265 * In order to ensure that mainboard setting does not disable L1 substates
266 * incorrectly, chip config parameter values are offset by 1 with 0 meaning
267 * use FSP UPD default. get_l1_substate_control() ensures that the right UPD
268 * value is set in fsp_params.
269 * 0: Use FSP UPD default
270 * 1: Disable L1 substates
271 * 2: Use L1.1
272 * 3: Use L1.2 (FSP UPD default)
273 */
274 static int get_l1_substate_control(enum L1_substates_control ctl)
275 {
276 if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT))
277 ctl = L1_SS_L1_2;
278 return ctl - 1;
279 }
280
281 __weak void mainboard_update_soc_chip_config(struct soc_intel_alderlake_config *config)
282 {
283 /* Override settings per board. */
284 }
285
286 static void fill_fsps_lpss_params(FSP_S_CONFIG *s_cfg,
287 const struct soc_intel_alderlake_config *config)
288 {
289 for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++)
290 s_cfg->SerialIoI2cMode[i] = config->SerialIoI2cMode[i];
291
292 for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) {
293 s_cfg->SerialIoSpiMode[i] = config->SerialIoGSpiMode[i];
294 s_cfg->SerialIoSpiCsMode[i] = config->SerialIoGSpiCsMode[i];
295 s_cfg->SerialIoSpiCsState[i] = config->SerialIoGSpiCsState[i];
296 }
297
298 for (int i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++)
299 s_cfg->SerialIoUartMode[i] = config->SerialIoUartMode[i];
300 }
301
302 static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg,
303 const struct soc_intel_alderlake_config *config)
304 {
305 const struct microcode *microcode_file;
306 size_t microcode_len;
307
308 /* Locate microcode and pass to FSP-S for 2nd microcode loading */
309 microcode_file = cbfs_map("cpu_microcode_blob.bin", &microcode_len);
310
311 if ((microcode_file != NULL) && (microcode_len != 0)) {
312 /* Update CPU Microcode patch base address/size */
313 s_cfg->MicrocodeRegionBase = (uint32_t)microcode_file;
314 s_cfg->MicrocodeRegionSize = (uint32_t)microcode_len;
315 }
316
317 /* Use coreboot MP PPI services if Kconfig is enabled */
318 if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI))
319 s_cfg->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
320 }
321
322 static void fill_fsps_igd_params(FSP_S_CONFIG *s_cfg,
323 const struct soc_intel_alderlake_config *config)
324 {
325 /* Load VBT before devicetree-specific config. */
326 s_cfg->GraphicsConfigPtr = (uintptr_t)vbt_get();
327
328 /* Check if IGD is present and fill Graphics init param accordingly */
329 s_cfg->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD);
330 s_cfg->LidStatus = CONFIG(RUN_FSP_GOP);
331 }
332
333 static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg,
334 const struct soc_intel_alderlake_config *config)
335 {
336 s_cfg->TcssAuxOri = config->TcssAuxOri;
337
338 /* Explicitly clear this field to avoid using defaults */
339 memset(s_cfg->IomTypeCPortPadCfg, 0, sizeof(s_cfg->IomTypeCPortPadCfg));
340
341 /*
342 * Set FSPS UPD ITbtConnectTopologyTimeoutInMs with value 0. FSP will
343 * evaluate this UPD value and skip sending command. There will be no
344 * delay for command completion.
345 */
346 s_cfg->ITbtConnectTopologyTimeoutInMs = 0;
347
348 /* D3Hot and D3Cold for TCSS */
349 s_cfg->D3HotEnable = !config->TcssD3HotDisable;
350 s_cfg->D3ColdEnable = !config->TcssD3ColdDisable;
351
352 s_cfg->UsbTcPortEn = 0;
353 for (int i = 0; i < MAX_TYPE_C_PORTS; i++) {
354 /* TCSS xHCI --> Root Hub --> Type-C Port */
355 const struct device_path port_path[] = {
356 {.type = DEVICE_PATH_PCI, .pci.devfn = SA_DEVFN_TCSS_XHCI},
357 {.type = DEVICE_PATH_USB, .usb.port_type = 0, .usb.port_id = 0},
358 {.type = DEVICE_PATH_USB, .usb.port_type = 3, .usb.port_id = i} };
359 const struct device *port = find_dev_nested_path(pci_root_bus(), port_path,
360 ARRAY_SIZE(port_path));
361
362 if (is_dev_enabled(port))
363 s_cfg->UsbTcPortEn |= BIT(i);
364 }
365 }
366
367 static void fill_fsps_chipset_lockdown_params(FSP_S_CONFIG *s_cfg,
368 const struct soc_intel_alderlake_config *config)
369 {
370 /* Chipset Lockdown */
371 if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) {
372 s_cfg->PchLockDownGlobalSmi = 0;
373 s_cfg->PchLockDownBiosInterface = 0;
374 s_cfg->PchUnlockGpioPads = 1;
375 s_cfg->RtcMemoryLock = 0;
376 } else {
377 s_cfg->PchLockDownGlobalSmi = 1;
378 s_cfg->PchLockDownBiosInterface = 1;
379 s_cfg->PchUnlockGpioPads = 0;
380 s_cfg->RtcMemoryLock = 1;
381 }
382
383 /* coreboot will send EOP before loading payload */
384 s_cfg->EndOfPostMessage = EOP_DISABLE;
385 }
386
387 static void fill_fsps_xhci_params(FSP_S_CONFIG *s_cfg,
388 const struct soc_intel_alderlake_config *config)
389 {
390 int i;
391 /* USB */
392 for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
393 s_cfg->PortUsb20Enable[i] = config->usb2_ports[i].enable;
394 s_cfg->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias;
395 s_cfg->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias;
396 s_cfg->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable;
397 s_cfg->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit;
398
399 if (config->usb2_ports[i].enable)
400 s_cfg->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
401 else
402 s_cfg->Usb2OverCurrentPin[i] = OC_SKIP;
403 }
404
405 for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
406 s_cfg->PortUsb30Enable[i] = config->usb3_ports[i].enable;
407 if (config->usb3_ports[i].enable)
408 s_cfg->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
409 else
410 s_cfg->Usb3OverCurrentPin[i] = OC_SKIP;
411
412 if (config->usb3_ports[i].tx_de_emp) {
413 s_cfg->Usb3HsioTxDeEmphEnable[i] = 1;
414 s_cfg->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp;
415 }
416 if (config->usb3_ports[i].tx_downscale_amp) {
417 s_cfg->Usb3HsioTxDownscaleAmpEnable[i] = 1;
418 s_cfg->Usb3HsioTxDownscaleAmp[i] =
419 config->usb3_ports[i].tx_downscale_amp;
420 }
421 }
422
423 for (i = 0; i < ARRAY_SIZE(config->tcss_ports); i++) {
424 if (config->tcss_ports[i].enable)
425 s_cfg->CpuUsb3OverCurrentPin[i] = config->tcss_ports[i].ocpin;
426 }
427 }
428
429 static void fill_fsps_xdci_params(FSP_S_CONFIG *s_cfg,
430 const struct soc_intel_alderlake_config *config)
431 {
432 s_cfg->XdciEnable = xdci_can_enable(PCH_DEVFN_USBOTG);
433 }
434
435 static void fill_fsps_uart_params(FSP_S_CONFIG *s_cfg,
436 const struct soc_intel_alderlake_config *config)
437 {
438 /* PCH UART selection for FSP Debug */
439 s_cfg->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
440 ASSERT(ARRAY_SIZE(s_cfg->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE);
441 s_cfg->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0;
442 }
443
444 static void fill_fsps_sata_params(FSP_S_CONFIG *s_cfg,
445 const struct soc_intel_alderlake_config *config)
446 {
447 /* SATA */
448 s_cfg->SataEnable = is_devfn_enabled(PCH_DEVFN_SATA);
449 if (s_cfg->SataEnable) {
450 s_cfg->SataMode = config->SataMode;
451 s_cfg->SataSalpSupport = config->SataSalpSupport;
452 memcpy(s_cfg->SataPortsEnable, config->SataPortsEnable,
453 sizeof(s_cfg->SataPortsEnable));
454 memcpy(s_cfg->SataPortsDevSlp, config->SataPortsDevSlp,
455 sizeof(s_cfg->SataPortsDevSlp));
456 }
457
458 /*
459 * Power Optimizer for SATA.
460 * SataPwrOptimizeDisable is default to 0.
461 * Boards not needing the optimizers explicitly disables them by setting
462 * these disable variables to 1 in devicetree overrides.
463 */
464 s_cfg->SataPwrOptEnable = !(config->SataPwrOptimizeDisable);
465 /*
466 * Enable DEVSLP Idle Timeout settings DmVal and DitoVal.
467 * SataPortsDmVal is the DITO multiplier. Default is 15.
468 * SataPortsDitoVal is the DEVSLP Idle Timeout (DITO), Default is 625ms.
469 * The default values can be changed from devicetree.
470 */
471 for (size_t i = 0; i < ARRAY_SIZE(config->SataPortsEnableDitoConfig); i++) {
472 if (config->SataPortsEnableDitoConfig[i]) {
473 s_cfg->SataPortsDmVal[i] = config->SataPortsDmVal[i];
474 s_cfg->SataPortsDitoVal[i] = config->SataPortsDitoVal[i];
475 }
476 }
477 }
478
479 static void fill_fsps_thermal_params(FSP_S_CONFIG *s_cfg,
480 const struct soc_intel_alderlake_config *config)
481 {
482 /* Enable TCPU for processor thermal control */
483 s_cfg->Device4Enable = is_devfn_enabled(SA_DEVFN_DPTF);
484
485 /* Set TccActivationOffset */
486 s_cfg->TccActivationOffset = config->tcc_offset;
487 }
488
489 static void fill_fsps_lan_params(FSP_S_CONFIG *s_cfg,
490 const struct soc_intel_alderlake_config *config)
491 {
492 /* LAN */
493 s_cfg->PchLanEnable = is_devfn_enabled(PCH_DEVFN_GBE);
494 }
495
496 static void fill_fsps_cnvi_params(FSP_S_CONFIG *s_cfg,
497 const struct soc_intel_alderlake_config *config)
498 {
499 /* CNVi */
500 s_cfg->CnviMode = is_devfn_enabled(PCH_DEVFN_CNVI_WIFI);
501 s_cfg->CnviBtCore = config->CnviBtCore;
502 s_cfg->CnviBtAudioOffload = config->CnviBtAudioOffload;
503 /* Assert if CNVi BT is enabled without CNVi being enabled. */
504 assert(s_cfg->CnviMode || !s_cfg->CnviBtCore);
505 /* Assert if CNVi BT offload is enabled without CNVi BT being enabled. */
506 assert(s_cfg->CnviBtCore || !s_cfg->CnviBtAudioOffload);
507 }
508
509 static void fill_fsps_vmd_params(FSP_S_CONFIG *s_cfg,
510 const struct soc_intel_alderlake_config *config)
511 {
512 /* VMD */
513 s_cfg->VmdEnable = is_devfn_enabled(SA_DEVFN_VMD);
514 }
515
516 static void fill_fsps_thc_params(FSP_S_CONFIG *s_cfg,
517 const struct soc_intel_alderlake_config *config)
518 {
519 /* THC */
520 s_cfg->ThcPort0Assignment = is_devfn_enabled(PCH_DEVFN_THC0) ? THC_0 : THC_NONE;
521 s_cfg->ThcPort1Assignment = is_devfn_enabled(PCH_DEVFN_THC1) ? THC_1 : THC_NONE;
522 }
523
524 static void fill_fsps_tbt_params(FSP_S_CONFIG *s_cfg,
525 const struct soc_intel_alderlake_config *config)
526 {
527 /* USB4/TBT */
528 for (int i = 0; i < ARRAY_SIZE(s_cfg->ITbtPcieRootPortEn); i++)
529 s_cfg->ITbtPcieRootPortEn[i] = is_devfn_enabled(SA_DEVFN_TBT(i));
530 }
531
532 static void fill_fsps_8254_params(FSP_S_CONFIG *s_cfg,
533 const struct soc_intel_alderlake_config *config)
534 {
535 /* Legacy 8254 timer support */
536 s_cfg->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER);
537 s_cfg->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER);
538 }
539
540 static void fill_fsps_storage_params(FSP_S_CONFIG *s_cfg,
541 const struct soc_intel_alderlake_config *config)
542 {
543 /* Enable Hybrid storage auto detection */
544 s_cfg->HybridStorageMode = config->HybridStorageMode;
545 }
546
547 static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg,
548 const struct soc_intel_alderlake_config *config)
549 {
550 uint32_t enable_mask = pcie_rp_enable_mask(get_pch_pcie_rp_table());
551 for (int i = 0; i < CONFIG_MAX_PCH_ROOT_PORTS; i++) {
552 if (!(enable_mask & BIT(i)))
553 continue;
554 const struct pcie_rp_config *rp_cfg = &config->pch_pcie_rp[i];
555 s_cfg->PcieRpL1Substates[i] =
556 get_l1_substate_control(rp_cfg->PcieRpL1Substates);
557 s_cfg->PcieRpLtrEnable[i] = !!(rp_cfg->flags & PCIE_RP_LTR);
558 s_cfg->PcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER);
559 s_cfg->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG);
560 s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT);
561 }
562 }
563
564 static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg,
565 const struct soc_intel_alderlake_config *config)
566 {
567 /*
568 * Power Optimizer for DMI
569 * DmiPwrOptimizeDisable is default to 0.
570 * Boards not needing the optimizers explicitly disables them by setting
571 * these disable variables to 1 in devicetree overrides.
572 */
573 s_cfg->PchPwrOptEnable = !(config->DmiPwrOptimizeDisable);
574 s_cfg->PmSupport = 1;
575 s_cfg->Hwp = 1;
576 s_cfg->Cx = 1;
577 s_cfg->PsOnEnable = 1;
578 /* Enable the energy efficient turbo mode */
579 s_cfg->EnergyEfficientTurbo = 1;
580 s_cfg->PkgCStateLimit = LIMIT_AUTO;
581 }
582
583 static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg,
584 const struct soc_intel_alderlake_config *config)
585 {
586 if (!assign_pci_irqs(irq_constraints, ARRAY_SIZE(irq_constraints)))
587 die("ERROR: Unable to assign PCI IRQs, and no _PRT table available\n");
588
589 size_t pch_count = 0;
590 const SI_PCH_DEVICE_INTERRUPT_CONFIG *upd_irqs = pci_irq_to_fsp(&pch_count);
591
592 s_cfg->DevIntConfigPtr = (UINT32)((uintptr_t)upd_irqs);
593 s_cfg->NumOfDevIntConfig = pch_count;
594 printk(BIOS_INFO, "IRQ: Using dynamically assigned PCI IO-APIC IRQs\n");
595 }
596
597 static void fill_fsps_fivr_params(FSP_S_CONFIG *s_cfg,
598 const struct soc_intel_alderlake_config *config)
599 {
600 /* PCH FIVR settings override */
601 if (!config->ext_fivr_settings.configure_ext_fivr)
602 return;
603
604 s_cfg->PchFivrExtV1p05RailEnabledStates =
605 config->ext_fivr_settings.v1p05_enable_bitmap;
606
607 s_cfg->PchFivrExtV1p05RailSupportedVoltageStates =
608 config->ext_fivr_settings.v1p05_supported_voltage_bitmap;
609
610 s_cfg->PchFivrExtVnnRailEnabledStates =
611 config->ext_fivr_settings.vnn_enable_bitmap;
612
613 s_cfg->PchFivrExtVnnRailSupportedVoltageStates =
614 config->ext_fivr_settings.vnn_supported_voltage_bitmap;
615
616 s_cfg->PchFivrExtVnnRailSxEnabledStates =
617 config->ext_fivr_settings.vnn_enable_bitmap;
618
619 /* Convert the voltages to increments of 2.5mv */
620 s_cfg->PchFivrExtV1p05RailVoltage =
621 (config->ext_fivr_settings.v1p05_voltage_mv * 10) / 25;
622
623 s_cfg->PchFivrExtVnnRailVoltage =
624 (config->ext_fivr_settings.vnn_voltage_mv * 10) / 25;
625
626 s_cfg->PchFivrExtVnnRailSxVoltage =
627 (config->ext_fivr_settings.vnn_sx_voltage_mv * 10 / 25);
628
629 s_cfg->PchFivrExtV1p05RailIccMaximum =
630 config->ext_fivr_settings.v1p05_icc_max_ma;
631
632 s_cfg->PchFivrExtVnnRailIccMaximum =
633 config->ext_fivr_settings.vnn_icc_max_ma;
634 }
635
636 static void arch_silicon_init_params(FSPS_ARCH_UPD *s_arch_cfg)
637 {
638 /* EnableMultiPhaseSiliconInit for running MultiPhaseSiInit */
639 s_arch_cfg->EnableMultiPhaseSiliconInit = 1;
640 }
641
642 static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg,
643 struct soc_intel_alderlake_config *config)
644 {
645 /* Override settings per board if required. */
646 mainboard_update_soc_chip_config(config);
647
648 const void (*fill_fsps_params[])(FSP_S_CONFIG *s_cfg,
649 const struct soc_intel_alderlake_config *config) = {
650 fill_fsps_lpss_params,
651 fill_fsps_cpu_params,
652 fill_fsps_igd_params,
653 fill_fsps_tcss_params,
654 fill_fsps_chipset_lockdown_params,
655 fill_fsps_xhci_params,
656 fill_fsps_xdci_params,
657 fill_fsps_uart_params,
658 fill_fsps_sata_params,
659 fill_fsps_thermal_params,
660 fill_fsps_lan_params,
661 fill_fsps_cnvi_params,
662 fill_fsps_vmd_params,
663 fill_fsps_thc_params,
664 fill_fsps_tbt_params,
665 fill_fsps_8254_params,
666 fill_fsps_storage_params,
667 fill_fsps_pcie_params,
668 fill_fsps_misc_power_params,
669 fill_fsps_irq_params,
670 fill_fsps_fivr_params,
671 };
672
673 for (size_t i = 0; i < ARRAY_SIZE(fill_fsps_params); i++)
674 fill_fsps_params[i](s_cfg, config);
675 }
676
677 /* UPD parameters to be initialized before SiliconInit */
678 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
679 {
680 struct soc_intel_alderlake_config *config;
681 FSP_S_CONFIG *s_cfg = &supd->FspsConfig;
682 FSPS_ARCH_UPD *s_arch_cfg = &supd->FspsArchUpd;
683
684 config = config_of_soc();
685 arch_silicon_init_params(s_arch_cfg);
686 soc_silicon_init_params(s_cfg, config);
687 mainboard_silicon_init_params(s_cfg);
688 }
689
690 /*
691 * Callbacks for SoC/Mainboard specific overrides for FspMultiPhaseSiInit
692 * This platform supports below MultiPhaseSIInit Phase(s):
693 * Phase | FSP return point | Purpose
694 * ------- + ------------------------------------------------ + -------------------------------
695 * 1 | After TCSS initialization completed | for TCSS specific init
696 */
697 void platform_fsp_multi_phase_init_cb(uint32_t phase_index)
698 {
699 switch (phase_index) {
700 case 1:
701 /* TCSS specific initialization here */
702 printk(BIOS_DEBUG, "FSP MultiPhaseSiInit %s/%s called\n",
703 __FILE__, __func__);
704
705 if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS)) {
706 const config_t *config = config_of_soc();
707 tcss_configure(config->typec_aux_bias_pads);
708 }
709 break;
710 default:
711 break;
712 }
713 }
714
715 /* Mainboard GPIO Configuration */
716 __weak void mainboard_silicon_init_params(FSP_S_CONFIG *s_cfg)
717 {
718 printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
719 }
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