src/soc/intel/apollolake/chip.h

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2015 Intel Corp.
   5  * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #ifndef _SOC_APOLLOLAKE_CHIP_H_
  19 #define _SOC_APOLLOLAKE_CHIP_H_
  20
  21 #define CLKREQ_DISABLED         0xf
  22
  23 /* Serial IRQ control. SERIRQ_QUIET is the default (0). */
  24 enum serirq_mode {
  25         SERIRQ_QUIET,
  26         SERIRQ_CONTINUOUS,
  27         SERIRQ_OFF,
  28 };
  29
  30 struct soc_intel_apollolake_config {
  31         /*
  32          * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has
  33          * four CLKREQ inputs, but six root ports. Root ports without an
  34          * associated CLKREQ signal must be marked with "CLKREQ_DISABLED"
  35          */
  36         uint8_t pcie_rp0_clkreq_pin;
  37         uint8_t pcie_rp1_clkreq_pin;
  38         uint8_t pcie_rp2_clkreq_pin;
  39         uint8_t pcie_rp3_clkreq_pin;
  40         uint8_t pcie_rp4_clkreq_pin;
  41         uint8_t pcie_rp5_clkreq_pin;
  42
  43         /* Configure serial IRQ (SERIRQ) line. */
  44         enum serirq_mode serirq_mode;
  45 };
  46
  47 #endif  /* _SOC_APOLLOLAKE_CHIP_H_ */