src/soc/intel/apollolake/chip.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2015 Intel Corp.
   5  * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)
   6  * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <bootstate.h>
  20 #include <cbmem.h>
  21 #include <console/console.h>
  22 #include <cpu/cpu.h>
  23 #include <device/device.h>
  24 #include <device/pci.h>
  25 #include <fsp/api.h>
  26 #include <fsp/util.h>
  27 #include <memrange.h>
  28 #include <soc/iomap.h>
  29 #include <soc/cpu.h>
  30 #include <soc/intel/common/vbt.h>
  31 #include <soc/nvs.h>
  32 #include <soc/pci_devs.h>
  33
  34 #include "chip.h"
  35
  36 static void *vbt;
  37 static struct region_device vbt_rdev;
  38
  39 static void pci_domain_set_resources(device_t dev)
  40 {
  41        assign_resources(dev->link_list);
  42 }
  43
  44 static struct device_operations pci_domain_ops = {
  45         .read_resources = pci_domain_read_resources,
  46         .set_resources = pci_domain_set_resources,
  47         .enable_resources = NULL,
  48         .init = NULL,
  49         .scan_bus = pci_domain_scan_bus,
  50         .ops_pci_bus = pci_bus_default_ops,
  51 };
  52
  53 static struct device_operations cpu_bus_ops = {
  54         .read_resources = DEVICE_NOOP,
  55         .set_resources = DEVICE_NOOP,
  56         .enable_resources = DEVICE_NOOP,
  57         .init = apollolake_init_cpus,
  58         .scan_bus = NULL,
  59 };
  60
  61 static void enable_dev(device_t dev)
  62 {
  63         /* Set the operations if it is a special bus type */
  64         if (dev->path.type == DEVICE_PATH_DOMAIN) {
  65                 dev->ops = &pci_domain_ops;
  66         } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
  67                 dev->ops = &cpu_bus_ops;
  68         }
  69 }
  70
  71 static void soc_init(void *data)
  72 {
  73         struct range_entry range;
  74         struct global_nvs_t *gnvs;
  75
  76         /* Save VBT info and mapping */
  77         if (locate_vbt(&vbt_rdev) != CB_ERR)
  78                 vbt = rdev_mmap_full(&vbt_rdev);
  79
  80         /* TODO: tigten this resource range */
  81         /* TODO: fix for S3 resume, as this would corrupt OS memory */
  82         range_entry_init(&range, 0x200000, 4ULL*GiB, 0);
  83         fsp_silicon_init(&range);
  84
  85         /* Allocate ACPI NVS in CBMEM */
  86         gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
  87 }
  88
  89 static void soc_final(void *data)
  90 {
  91         if (vbt)
  92                 rdev_munmap(&vbt_rdev, vbt);
  93 }
  94
  95 void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
  96 {
  97         struct FSP_S_CONFIG *silconfig = &silupd->FspsConfig;
  98         static struct soc_intel_apollolake_config *cfg;
  99
 100         /* Load VBT before devicetree-specific config. */
 101         silconfig->GraphicsConfigPtr = (uintptr_t)vbt;
 102
 103         struct device *dev = NB_DEV_ROOT;
 104         if (!dev || !dev->chip_info) {
 105                 printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
 106                 return;
 107         }
 108
 109         cfg = dev->chip_info;
 110
 111         silconfig->PcieRpClkReqNumber[0] = cfg->pcie_rp0_clkreq_pin;
 112         silconfig->PcieRpClkReqNumber[1] = cfg->pcie_rp1_clkreq_pin;
 113         silconfig->PcieRpClkReqNumber[2] = cfg->pcie_rp2_clkreq_pin;
 114         silconfig->PcieRpClkReqNumber[3] = cfg->pcie_rp3_clkreq_pin;
 115         silconfig->PcieRpClkReqNumber[4] = cfg->pcie_rp4_clkreq_pin;
 116         silconfig->PcieRpClkReqNumber[5] = cfg->pcie_rp5_clkreq_pin;
 117
 118         /* Our defaults may not match FSP defaults, so set them explicitly */
 119         silconfig->AcpiBase = ACPI_PMIO_BASE;
 120         /* First 4k in BAR0 is used for IPC, real registers start at 4k offset */
 121         silconfig->PmcBase = PMC_BAR0 + 0x1000;
 122         silconfig->P2sbBase = P2SB_BAR;
 123 }
 124
 125 struct chip_operations soc_intel_apollolake_ops = {
 126         CHIP_NAME("Intel Apollolake SOC")
 127         .enable_dev = &enable_dev,
 128         .init = &soc_init,
 129         .final = &soc_final
 130 };
 131
 132 static void fsp_notify_dummy(void *arg)
 133 {
 134
 135         enum fsp_notify_phase ph = (enum fsp_notify_phase) arg;
 136
 137         if (fsp_notify(ph) != FSP_SUCCESS)
 138                 printk(BIOS_CRIT, "FspNotify failed!\n");
 139 }
 140
 141 BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, fsp_notify_dummy,
 142                                                 (void *) AFTER_PCI_ENUM);
 143 BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, fsp_notify_dummy,
 144                                                 (void *) READY_TO_BOOT);
 145 BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, fsp_notify_dummy,
 146                                                 (void *) READY_TO_BOOT);