2 * This file is part of the coreboot project.
4 * Copyright (C) 2016 Intel Corp.
5 * Copyright 2016 Google Inc.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
20 #include <program_loading.h>
24 * This file supports the necessary hoops one needs to jump through since
25 * early FSP component and early stages are running from cache-as-ram.
28 static void flush_l1d_to_l2(void)
30 msr_t msr
= rdmsr(MSR_POWER_MISC
);
32 wrmsr(MSR_POWER_MISC
, msr
);
35 static inline int is_car_addr(uintptr_t addr
)
37 return ((addr
>= CONFIG_DCACHE_RAM_BASE
) &&
38 (addr
< (CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE
)));
41 void platform_segment_loaded(uintptr_t start
, size_t size
, int flags
)
43 /* Bail out if this is not the final segment. */
44 if (!(flags
& SEG_FINAL
))
47 char start_car_check
= is_car_addr(start
);
48 char end_car_check
= is_car_addr(start
+ size
- 1);
50 /* Bail out if loaded program segment does not lie in CAR region. */
51 if (!start_car_check
&& !end_car_check
)
54 /* Loaded program segment should lie entirely within CAR region. */
55 assert (start_car_check
&& end_car_check
);