src/soc/intel/xeon_sp/skx/soc_acpi.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <acpi/acpigen.h>
   4 #include <arch/smp/mpspec.h>
   5 #include <assert.h>
   6 #include <cpu/intel/turbo.h>
   7 #include <device/mmio.h>
   8 #include <device/pci.h>
   9 #include <intelblocks/acpi.h>
  10 #include <soc/acpi.h>
  11 #include <soc/cpu.h>
  12 #include <soc/iomap.h>
  13 #include <soc/msr.h>
  14 #include <soc/pci_devs.h>
  15 #include <soc/pm.h>
  16 #include <soc/soc_util.h>
  17 #include <soc/util.h>
  18
  19 int soc_madt_sci_irq_polarity(int sci)
  20 {
  21         if (sci >= 20)
  22                 return MP_IRQ_POLARITY_LOW;
  23         else
  24                 return MP_IRQ_POLARITY_HIGH;
  25 }
  26
  27 uint32_t soc_read_sci_irq_select(void)
  28 {
  29         struct device *dev = PCH_DEV_PMC;
  30
  31         if (!dev)
  32                 return 0;
  33
  34         return pci_read_config32(dev, PMC_ACPI_CNT);
  35 }
  36
  37 void soc_fill_fadt(acpi_fadt_t *fadt)
  38 {
  39         const uint16_t pmbase = ACPI_BASE_ADDRESS;
  40
  41         /* Fix flags set by common/block/acpi/acpi.c acpi_fill_fadt() */
  42         fadt->flags &=  ~(ACPI_FADT_SEALED_CASE);
  43         fadt->flags |= ACPI_FADT_SLEEP_TYPE;
  44
  45         fadt->pm2_cnt_blk = pmbase + PM2_CNT;
  46         fadt->pm_tmr_blk = pmbase + PM1_TMR;
  47
  48         fadt->pm2_cnt_len = 1;
  49         fadt->pm_tmr_len = 4;
  50
  51         /* RTC Registers */
  52         fadt->mon_alrm = 0x00;
  53         fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
  54
  55         /* PM2 Control Registers */
  56         fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
  57         fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
  58         fadt->x_pm2_cnt_blk.bit_offset = 0;
  59         fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
  60         fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
  61         fadt->x_pm2_cnt_blk.addrh = 0x00;
  62
  63         /* PM1 Timer Register */
  64         fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
  65         fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
  66         fadt->x_pm_tmr_blk.bit_offset = 0;
  67         fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
  68         fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
  69         fadt->x_pm_tmr_blk.addrh = 0x00;
  70
  71 }
  72
  73 void uncore_inject_dsdt(const struct device *device)
  74 {
  75         const IIO_UDS *hob = get_iio_uds();
  76
  77         /* Only add RTxx entries once. */
  78         if (device->bus->secondary != 0)
  79                 return;
  80
  81         acpigen_write_scope("\\_SB");
  82         for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) {
  83                 IIO_RESOURCE_INSTANCE iio_resource =
  84                         hob->PlatformData.IIO_resource[socket];
  85                 for (int stack = 0; stack <= PSTACK2; ++stack) {
  86                         const STACK_RES *ri = &iio_resource.StackRes[stack];
  87                         char rtname[16];
  88                         snprintf(rtname, sizeof(rtname), "RT%02x",
  89                                 (socket*MAX_IIO_STACK)+stack);
  90
  91                         acpigen_write_name(rtname);
  92                         printk(BIOS_DEBUG, "\tCreating ResourceTemplate %s for socket: %d, stack: %d\n",
  93                                 rtname, socket, stack);
  94
  95                         acpigen_write_resourcetemplate_header();
  96
  97                         /* bus resource */
  98                         acpigen_resource_word(2, 0xc, 0, 0, ri->BusBase, ri->BusLimit,
  99                                 0x0, (ri->BusLimit - ri->BusBase + 1));
 100
 101                         // additional io resources on socket 0 bus 0
 102                         if (socket == 0 && stack == 0) {
 103                                 /* ACPI 6.4.2.5 I/O Port Descriptor */
 104                                 acpigen_write_io16(0xCF8, 0xCFF, 0x1, 0x8, 1);
 105
 106                                 /* IO decode  CF8-CFF */
 107                                 acpigen_resource_word(1, 0xc, 0x3, 0, 0x0000, 0x03AF,
 108                                         0, 0x03B0);
 109                                 acpigen_resource_word(1, 0xc, 0x3, 0, 0x03E0, 0x0CF7,
 110                                         0, 0x0918);
 111                                 acpigen_resource_word(1, 0xc, 0x3, 0, 0x03B0, 0x03BB,
 112                                         0, 0x000C);
 113                                 acpigen_resource_word(1, 0xc, 0x3, 0, 0x03C0, 0x03DF,
 114                                         0, 0x0020);
 115                         }
 116
 117                         /* IO resource */
 118                         acpigen_resource_word(1, 0xc, 0x3, 0, ri->PciResourceIoBase,
 119                                 ri->PciResourceIoLimit, 0x0,
 120                                 (ri->PciResourceIoLimit - ri->PciResourceIoBase + 1));
 121
 122                         // additional mem32 resources on socket 0 bus 0
 123                         if (socket == 0 && stack == 0) {
 124                                 acpigen_resource_dword(0, 0xc, 3, 0, VGA_BASE_ADDRESS,
 125                                         (VGA_BASE_ADDRESS + VGA_BASE_SIZE - 1), 0x0,
 126                                         VGA_BASE_SIZE);
 127                                 acpigen_resource_dword(0, 0xc, 1, 0, SPI_BASE_ADDRESS,
 128                                         (SPI_BASE_ADDRESS + SPI_BASE_SIZE - 1), 0x0,
 129                                         SPI_BASE_SIZE);
 130                         }
 131
 132                         /* Mem32 resource */
 133                         acpigen_resource_dword(0, 0xc, 1, 0, ri->PciResourceMem32Base,
 134                                 ri->PciResourceMem32Limit, 0x0,
 135                                 (ri->PciResourceMem32Limit - ri->PciResourceMem32Base + 1));
 136
 137                         /* Mem64 resource */
 138                         acpigen_resource_qword(0, 0xc, 1, 0, ri->PciResourceMem64Base,
 139                                 ri->PciResourceMem64Limit, 0x0,
 140                                 (ri->PciResourceMem64Limit - ri->PciResourceMem64Base + 1));
 141
 142                         acpigen_write_resourcetemplate_footer();
 143                 }
 144         }
 145         acpigen_pop_len();
 146 }
 147
 148 void soc_power_states_generation(int core, int cores_per_package)
 149 {
 150 }
 151
 152 unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current)
 153 {
 154         struct device *cpu;
 155         uint8_t num_cpus = 0;
 156
 157         for (cpu = all_devices; cpu; cpu = cpu->next) {
 158                 if (!is_enabled_cpu(cpu))
 159                         continue;
 160                 current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current,
 161                         num_cpus, cpu->path.apic.apic_id);
 162                 num_cpus++;
 163         }
 164
 165         return current;
 166 }