src/soc/intel/common/block/graphics/graphics.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <acpi/acpi.h>
   4 #include <assert.h>
   5 #include <bootmode.h>
   6 #include <console/console.h>
   7 #include <device/mmio.h>
   8 #include <device/pci.h>
   9 #include <device/pci_ids.h>
  10 #include <drivers/intel/gma/i915.h>
  11 #include <drivers/intel/gma/libgfxinit.h>
  12 #include <drivers/intel/gma/opregion.h>
  13 #include <intelblocks/cfg.h>
  14 #include <intelblocks/graphics.h>
  15 #include <fsp/graphics.h>
  16 #include <soc/pci_devs.h>
  17 #include <types.h>
  18
  19 /* Display Type:
  20 *  0 - only internal display aka eDP attached
  21 *  1 - only external display aka HDMI/USB-C attached
  22 *  2 - dual display aka both internal and external display attached
  23 */
  24 enum display_type {
  25         INTERNAL_DISPLAY_ONLY,
  26         EXTERNAL_DISPLAY_ONLY,
  27         DUAL_DISPLAY,
  28 };
  29
  30 #define GFX_MBUS_CTL            0x4438C
  31 #define GFX_MBUS_SEL(x)         (GFX_MBUS_CTL + (x))
  32 #define GFX_MBUS_JOIN           BIT(31)
  33 #define GFX_MBUS_HASHING_MODE   BIT(30)
  34 #define GFX_MBUS_JOIN_PIPE_SEL  (BIT(28) | BIT(27) | BIT(26))
  35
  36 /* SoC Overrides */
  37 __weak void graphics_soc_panel_init(struct device *dev)
  38 {
  39         /*
  40          * User needs to implement SoC override in case wishes
  41          * to perform certain specific graphics initialization
  42          */
  43 }
  44
  45 __weak const struct i915_gpu_controller_info *
  46 intel_igd_get_controller_info(const struct device *device)
  47 {
  48         return NULL;
  49 }
  50
  51 static uint32_t graphics_get_ddi_func_ctrl(unsigned long reg)
  52 {
  53         uint32_t ddi_func_ctrl = graphics_gtt_read(reg);
  54         ddi_func_ctrl &= TRANS_DDI_PORT_MASK;
  55
  56         return ddi_func_ctrl;
  57 }
  58
  59 /*
  60  * Transcoders contain the timing generators for eDP, DP, and HDMI interfaces.
  61  * Intel transcoders are based on Quick Sync Video, which offloads video
  62  * encoding and decoding tasks from the CPU to the GPU.
  63  *
  64  * On Intel silicon, there are four display pipes (DDI-A to DDI-D) that support
  65  * blending, color adjustments, scaling, and dithering.
  66  *
  67  * From the display block diagram perspective, the front end of the display
  68  * contains the pipes. The pipes connect to the transcoder. The transcoder
  69  * (except for wireless) connects to the DDIs to drive the IO/PHY.
  70  *
  71  * This logic checks if the DDI-A port is attached to the transcoder and
  72  * enabled (bit 27). Traditionally, the on-board display (eDP) is attached to DDI-A.
  73  * If the above conditions is met, then the on-board display is present and enabled.
  74  *
  75  * On platforms without an on-board display (i.e., value at bits 27-30 is between 2-9),
  76  * meaning that DDI-A (eDP) is not enabled.
  77  *
  78  * Additionally, if bits 27-30 are all set to 0, this means that no DDI ports
  79  * are enabled, and there is no display.
  80  *
  81  * Consider external display is present and enabled, if eDP/DDI-A is not enabled
  82  * and transcoder is attached to any DDI port (bits 27-30 are not zero).
  83  */
  84 static enum display_type get_external_display_status(void)
  85 {
  86         /* Read the transcoder register for DDI-A (eDP) */
  87         uint32_t ddi_a_func_ctrl = graphics_get_ddi_func_ctrl(TRANS_DDI_FUNC_CTL_A);
  88         /* Read the transcoder register for DDI-B (HDMI) */
  89         uint32_t ddi_b_func_ctrl = graphics_get_ddi_func_ctrl(TRANS_DDI_FUNC_CTL_B);
  90
  91         /*
  92          * Check if transcoder is none or connected to DDI-A port (aka eDP).
  93          * Report no external display in both cases.
  94          */
  95         if (ddi_a_func_ctrl == TRANS_DDI_PORT_NONE) {
  96                 return INTERNAL_DISPLAY_ONLY;
  97         } else {
  98                 if (ddi_a_func_ctrl == TRANS_DDI_SELECT_PORT(PORT_A) &&
  99                          (ddi_b_func_ctrl == TRANS_DDI_SELECT_PORT(PORT_B)
 100 #if CONFIG(INTEL_GMA_VERSION_2)
 101                          || ddi_b_func_ctrl == TRANS_DDI_SELECT_PORT(PORT_USB_C1)
 102                          || ddi_b_func_ctrl == TRANS_DDI_SELECT_PORT(PORT_USB_C2)
 103                          || ddi_b_func_ctrl == TRANS_DDI_SELECT_PORT(PORT_USB_C3)
 104                          || ddi_b_func_ctrl == TRANS_DDI_SELECT_PORT(PORT_USB_C4)
 105 #endif
 106                 )) {
 107                         /*
 108                          * Dual display detected: both DDI-A(eDP) and
 109                          * DDI-B(HDMI) pipes are active
 110                          */
 111                         return DUAL_DISPLAY;
 112                 } else {
 113                         if (ddi_a_func_ctrl == TRANS_DDI_SELECT_PORT(PORT_A))
 114                                 return INTERNAL_DISPLAY_ONLY;
 115                         else
 116                                 return EXTERNAL_DISPLAY_ONLY;
 117                 }
 118         }
 119 }
 120
 121 /* Check and report if an external display is attached */
 122 int fsp_soc_report_external_display(void)
 123 {
 124         return graphics_get_framebuffer_address() && get_external_display_status();
 125 }
 126
 127 static void gma_init(struct device *const dev)
 128 {
 129         intel_gma_init_igd_opregion();
 130
 131         /* SoC specific panel init/configuration.
 132            If FSP has already run/configured the IGD, we can assume the
 133            panel/backlight control have already been set up sufficiently
 134            and that we shouldn't attempt to reconfigure things. */
 135         if (!CONFIG(RUN_FSP_GOP))
 136                 graphics_soc_panel_init(dev);
 137
 138         if (CONFIG(SOC_INTEL_CONFIGURE_DDI_A_4_LANES) && !acpi_is_wakeup_s3()) {
 139                 const u32 ddi_buf_ctl = graphics_gtt_read(DDI_BUF_CTL_A);
 140                 /* Only program if the buffer is not enabled yet. */
 141                 if (!(ddi_buf_ctl & DDI_BUF_CTL_ENABLE))
 142                         graphics_gtt_write(DDI_BUF_CTL_A, ddi_buf_ctl | DDI_A_4_LANES);
 143         }
 144
 145         /*
 146          * GFX PEIM module inside FSP binary is taking care of graphics
 147          * initialization based on RUN_FSP_GOP Kconfig option and input
 148          * VBT file. Need to report the framebuffer info after PCI enumeration.
 149          *
 150          * In case of non-FSP solution, SoC need to select another
 151          * Kconfig to perform GFX initialization.
 152          */
 153         if (CONFIG(RUN_FSP_GOP) && display_init_required()) {
 154                 const struct soc_intel_common_config *config = chip_get_common_soc_structure();
 155                 fsp_report_framebuffer_info(graphics_get_framebuffer_address(),
 156                                             config->panel_orientation);
 157                 return;
 158         }
 159
 160         if (!CONFIG(NO_GFX_INIT))
 161                 pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
 162
 163         if (CONFIG(MAINBOARD_USE_LIBGFXINIT)) {
 164                 if (!acpi_is_wakeup_s3() && display_init_required()) {
 165                         int lightup_ok;
 166                         gma_gfxinit(&lightup_ok);
 167                         gfx_set_init_done(lightup_ok);
 168                 }
 169         } else {
 170                 /* Initialize PCI device, load/execute BIOS Option ROM */
 171                 pci_dev_init(dev);
 172         }
 173 }
 174
 175 static void gma_generate_ssdt(const struct device *device)
 176 {
 177         const struct i915_gpu_controller_info *gfx = intel_igd_get_controller_info(device);
 178
 179         if (gfx)
 180                 drivers_intel_gma_displays_ssdt_generate(gfx);
 181 }
 182
 183 static int is_graphics_disabled(struct device *dev)
 184 {
 185         /* Check if Graphics PCI device is disabled */
 186         if (!dev || !dev->enabled)
 187                 return 1;
 188
 189         return 0;
 190 }
 191
 192 static uintptr_t graphics_get_bar(struct device *dev, unsigned long index)
 193 {
 194         struct resource *gm_res;
 195
 196         gm_res = probe_resource(dev, index);
 197         if (!gm_res)
 198                 return 0;
 199
 200         return gm_res->base;
 201 }
 202
 203 uintptr_t graphics_get_framebuffer_address(void)
 204 {
 205         uintptr_t memory_base;
 206         struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD);
 207
 208         if (is_graphics_disabled(dev))
 209                 return 0;
 210
 211         memory_base = graphics_get_bar(dev, PCI_BASE_ADDRESS_2);
 212         if (!memory_base)
 213                 die_with_post_code(POSTCODE_HW_INIT_FAILURE,
 214                                    "Graphic memory bar2 is not programmed!");
 215
 216         memory_base += CONFIG_SOC_INTEL_GFX_FRAMEBUFFER_OFFSET;
 217
 218         return memory_base;
 219 }
 220
 221 static uintptr_t graphics_get_gtt_base(void)
 222 {
 223         static uintptr_t gtt_base;
 224         struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD);
 225
 226         if (is_graphics_disabled(dev))
 227                 die("IGD is disabled!");
 228         /*
 229          * GFX PCI config space offset 0x10 know as Graphics
 230          * Translation Table Memory Mapped Range Address
 231          * (GTTMMADR)
 232          */
 233         if (!gtt_base) {
 234                 gtt_base = graphics_get_bar(dev, PCI_BASE_ADDRESS_0);
 235                 if (!gtt_base)
 236                         die_with_post_code(POSTCODE_HW_INIT_FAILURE,
 237                                            "GTTMMADR is not programmed!");
 238         }
 239         return gtt_base;
 240 }
 241
 242 uint32_t graphics_gtt_read(unsigned long reg)
 243 {
 244         return read32p(graphics_get_gtt_base() + reg);
 245 }
 246
 247 void graphics_gtt_write(unsigned long reg, uint32_t data)
 248 {
 249         write32p(graphics_get_gtt_base() + reg, data);
 250 }
 251
 252 void graphics_gtt_rmw(unsigned long reg, uint32_t andmask, uint32_t ormask)
 253 {
 254         uint32_t val = graphics_gtt_read(reg);
 255         val &= andmask;
 256         val |= ormask;
 257         graphics_gtt_write(reg, val);
 258 }
 259
 260 static void graphics_dev_read_resources(struct device *dev)
 261 {
 262         pci_dev_read_resources(dev);
 263
 264         if (CONFIG(SOC_INTEL_GFX_NON_PREFETCHABLE_MMIO)) {
 265                 struct resource *res_bar0 = find_resource(dev, PCI_BASE_ADDRESS_0);
 266                 if (res_bar0->flags & IORESOURCE_PREFETCH)
 267                         res_bar0->flags &= ~IORESOURCE_PREFETCH;
 268         }
 269
 270         /*
 271          * If libhwbase static MMIO driver is used, IGD BAR 0 has to be set to
 272          * CONFIG_GFX_GMA_DEFAULT_MMIO for the libgfxinit to operate properly.
 273          */
 274         if (CONFIG(MAINBOARD_USE_LIBGFXINIT) && CONFIG(HWBASE_STATIC_MMIO)) {
 275                 struct resource *res_bar0 = find_resource(dev, PCI_BASE_ADDRESS_0);
 276                 res_bar0->base = CONFIG_GFX_GMA_DEFAULT_MMIO;
 277                 res_bar0->flags |= IORESOURCE_ASSIGNED;
 278                 pci_dev_set_resources(dev);
 279                 res_bar0->flags |= IORESOURCE_FIXED;
 280         }
 281 }
 282
 283 static void graphics_join_mbus(void)
 284 {
 285         enum display_type type = get_external_display_status();
 286         uint32_t hashing_mode = 0;  /* 2x2 */
 287         if (type == INTERNAL_DISPLAY_ONLY) {
 288                 hashing_mode = GFX_MBUS_HASHING_MODE; /* 1x4 */
 289                 /* Only eDP pipes is joining the MBUS */
 290                 graphics_gtt_rmw(GFX_MBUS_SEL(PIPE_A), PIPE_A, GFX_MBUS_JOIN | hashing_mode);
 291         } else if (type == DUAL_DISPLAY) {
 292                 /* All pipes are joining the MBUS */
 293                 graphics_gtt_rmw(GFX_MBUS_SEL(PIPE_A), PIPE_A, GFX_MBUS_JOIN | hashing_mode);
 294                 graphics_gtt_rmw(GFX_MBUS_SEL(PIPE_B), PIPE_B, GFX_MBUS_JOIN | hashing_mode);
 295                 graphics_gtt_rmw(GFX_MBUS_SEL(PIPE_C), PIPE_C, GFX_MBUS_JOIN | hashing_mode);
 296 #if CONFIG(INTEL_GMA_VERSION_2)
 297                 graphics_gtt_rmw(GFX_MBUS_SEL(PIPE_D), PIPE_D, GFX_MBUS_JOIN | hashing_mode);
 298 #endif
 299         } else {
 300                 /* No pipe joins the MBUS */
 301                 graphics_gtt_rmw(GFX_MBUS_CTL, GFX_MBUS_JOIN_PIPE_SEL,
 302                                  GFX_MBUS_JOIN | hashing_mode);
 303         }
 304 }
 305
 306 static void graphics_dev_final(struct device *dev)
 307 {
 308         pci_dev_request_bus_master(dev);
 309
 310         /*
 311          * Call function to join the MBUS if GFX PEIM module inside FSP
 312          * binary is taking care of graphics initialization based on
 313          * RUN_FSP_GOP config option.
 314          *
 315          * Skip FW joining the MBUS in case of non-FSP solution.
 316          */
 317         if (CONFIG(RUN_FSP_GOP) && CONFIG(SOC_INTEL_GFX_MBUS_JOIN) && display_init_required())
 318                 graphics_join_mbus();
 319 }
 320
 321 const struct device_operations graphics_ops = {
 322         .read_resources         = graphics_dev_read_resources,
 323         .set_resources          = pci_dev_set_resources,
 324         .enable_resources       = pci_dev_enable_resources,
 325         .init                   = gma_init,
 326         .final                  = graphics_dev_final,
 327         .ops_pci                = &pci_dev_ops_pci,
 328 #if CONFIG(HAVE_ACPI_TABLES)
 329         .acpi_fill_ssdt         = gma_generate_ssdt,
 330 #endif
 331         .scan_bus               = scan_generic_bus,
 332 };
 333
 334 static const unsigned short pci_device_ids[] = {
 335         PCI_DID_INTEL_LNL_M_GT2,
 336         PCI_DID_INTEL_RPL_U_GT1,
 337         PCI_DID_INTEL_RPL_U_GT2,
 338         PCI_DID_INTEL_RPL_U_GT3,
 339         PCI_DID_INTEL_RPL_U_GT4,
 340         PCI_DID_INTEL_RPL_U_GT5,
 341         PCI_DID_INTEL_RPL_P_GT1,
 342         PCI_DID_INTEL_RPL_P_GT2,
 343         PCI_DID_INTEL_RPL_P_GT3,
 344         PCI_DID_INTEL_RPL_P_GT4,
 345         PCI_DID_INTEL_RPL_P_GT5,
 346         PCI_DID_INTEL_MTL_M_GT2,
 347         PCI_DID_INTEL_MTL_P_GT2_1,
 348         PCI_DID_INTEL_MTL_P_GT2_2,
 349         PCI_DID_INTEL_MTL_P_GT2_3,
 350         PCI_DID_INTEL_MTL_P_GT2_4,
 351         PCI_DID_INTEL_APL_IGD_HD_505,
 352         PCI_DID_INTEL_APL_IGD_HD_500,
 353         PCI_DID_INTEL_CNL_GT2_ULX_1,
 354         PCI_DID_INTEL_CNL_GT2_ULX_2,
 355         PCI_DID_INTEL_CNL_GT2_ULX_3,
 356         PCI_DID_INTEL_CNL_GT2_ULX_4,
 357         PCI_DID_INTEL_CNL_GT2_ULT_1,
 358         PCI_DID_INTEL_CNL_GT2_ULT_2,
 359         PCI_DID_INTEL_CNL_GT2_ULT_3,
 360         PCI_DID_INTEL_CNL_GT2_ULT_4,
 361         PCI_DID_INTEL_GLK_IGD,
 362         PCI_DID_INTEL_GLK_IGD_EU12,
 363         PCI_DID_INTEL_WHL_GT1_ULT_1,
 364         PCI_DID_INTEL_WHL_GT2_ULT_1,
 365         PCI_DID_INTEL_AML_GT2_ULX,
 366         PCI_DID_INTEL_CFL_H_GT2,
 367         PCI_DID_INTEL_CFL_H_XEON_GT2,
 368         PCI_DID_INTEL_CFL_S_GT1_1,
 369         PCI_DID_INTEL_CFL_S_GT1_2,
 370         PCI_DID_INTEL_CFL_S_GT2_1,
 371         PCI_DID_INTEL_CFL_S_GT2_2,
 372         PCI_DID_INTEL_CFL_S_GT2_3,
 373         PCI_DID_INTEL_CFL_S_GT2_4,
 374         PCI_DID_INTEL_CFL_S_GT2_5,
 375         PCI_DID_INTEL_CML_GT1_ULT_1,
 376         PCI_DID_INTEL_CML_GT1_ULT_2,
 377         PCI_DID_INTEL_CML_GT2_ULT_1,
 378         PCI_DID_INTEL_CML_GT2_ULT_2,
 379         PCI_DID_INTEL_CML_GT1_ULT_3,
 380         PCI_DID_INTEL_CML_GT1_ULT_4,
 381         PCI_DID_INTEL_CML_GT2_ULT_5,
 382         PCI_DID_INTEL_CML_GT2_ULT_6,
 383         PCI_DID_INTEL_CML_GT2_ULT_7,
 384         PCI_DID_INTEL_CML_GT2_ULT_8,
 385         PCI_DID_INTEL_CML_GT2_ULT_3,
 386         PCI_DID_INTEL_CML_GT2_ULT_4,
 387         PCI_DID_INTEL_CML_GT1_ULX_1,
 388         PCI_DID_INTEL_CML_GT2_ULX_1,
 389         PCI_DID_INTEL_CML_GT1_S_1,
 390         PCI_DID_INTEL_CML_GT1_S_2,
 391         PCI_DID_INTEL_CML_GT2_S_1,
 392         PCI_DID_INTEL_CML_GT2_S_2,
 393         PCI_DID_INTEL_CML_GT1_H_1,
 394         PCI_DID_INTEL_CML_GT1_H_2,
 395         PCI_DID_INTEL_CML_GT2_H_1,
 396         PCI_DID_INTEL_CML_GT2_H_2,
 397         PCI_DID_INTEL_CML_GT2_S_G0,
 398         PCI_DID_INTEL_CML_GT2_S_P0,
 399         PCI_DID_INTEL_CML_GT2_H_R0,
 400         PCI_DID_INTEL_CML_GT2_H_R1,
 401         PCI_DID_INTEL_TGL_GT0,
 402         PCI_DID_INTEL_TGL_GT1_H_32,
 403         PCI_DID_INTEL_TGL_GT1_H_16,
 404         PCI_DID_INTEL_TGL_GT2_ULT,
 405         PCI_DID_INTEL_TGL_GT2_ULX,
 406         PCI_DID_INTEL_TGL_GT3_ULT,
 407         PCI_DID_INTEL_TGL_GT2_ULT_1,
 408         PCI_DID_INTEL_EHL_GT1_1,
 409         PCI_DID_INTEL_EHL_GT2_1,
 410         PCI_DID_INTEL_EHL_GT1_2,
 411         PCI_DID_INTEL_EHL_GT2_2,
 412         PCI_DID_INTEL_EHL_GT1_2_1,
 413         PCI_DID_INTEL_EHL_GT1_3,
 414         PCI_DID_INTEL_EHL_GT2_3,
 415         PCI_DID_INTEL_JSL_GT1,
 416         PCI_DID_INTEL_JSL_GT2,
 417         PCI_DID_INTEL_JSL_GT3,
 418         PCI_DID_INTEL_JSL_GT4,
 419         PCI_DID_INTEL_ADL_GT0,
 420         PCI_DID_INTEL_ADL_GT1,
 421         PCI_DID_INTEL_ADL_GT1_1,
 422         PCI_DID_INTEL_ADL_GT1_2,
 423         PCI_DID_INTEL_ADL_GT1_3,
 424         PCI_DID_INTEL_ADL_GT1_4,
 425         PCI_DID_INTEL_ADL_GT1_5,
 426         PCI_DID_INTEL_ADL_GT1_6,
 427         PCI_DID_INTEL_ADL_GT1_7,
 428         PCI_DID_INTEL_ADL_GT1_8,
 429         PCI_DID_INTEL_ADL_GT1_9,
 430         PCI_DID_INTEL_ADL_P_GT2,
 431         PCI_DID_INTEL_ADL_P_GT2_1,
 432         PCI_DID_INTEL_ADL_P_GT2_2,
 433         PCI_DID_INTEL_ADL_P_GT2_3,
 434         PCI_DID_INTEL_ADL_P_GT2_4,
 435         PCI_DID_INTEL_ADL_P_GT2_5,
 436         PCI_DID_INTEL_ADL_P_GT2_6,
 437         PCI_DID_INTEL_ADL_P_GT2_7,
 438         PCI_DID_INTEL_ADL_P_GT2_8,
 439         PCI_DID_INTEL_ADL_P_GT2_9,
 440         PCI_DID_INTEL_ADL_S_GT1,
 441         PCI_DID_INTEL_ADL_S_GT1_1,
 442         PCI_DID_INTEL_ADL_S_GT2,
 443         PCI_DID_INTEL_ADL_S_GT2_1,
 444         PCI_DID_INTEL_ADL_S_GT2_2,
 445         PCI_DID_INTEL_ADL_M_GT1,
 446         PCI_DID_INTEL_ADL_M_GT2,
 447         PCI_DID_INTEL_ADL_M_GT3,
 448         PCI_DID_INTEL_ADL_N_GT1,
 449         PCI_DID_INTEL_ADL_N_GT2,
 450         PCI_DID_INTEL_ADL_N_GT3,
 451         PCI_DID_INTEL_RPL_S_GT0,
 452         PCI_DID_INTEL_RPL_S_GT1_1,
 453         PCI_DID_INTEL_RPL_S_GT1_2,
 454         PCI_DID_INTEL_RPL_S_GT1_3,
 455         PCI_DID_INTEL_RPL_HX_GT1,
 456         PCI_DID_INTEL_RPL_HX_GT2,
 457         PCI_DID_INTEL_RPL_HX_GT3,
 458         PCI_DID_INTEL_RPL_HX_GT4,
 459         PCI_DID_INTEL_TWL_GT1_1,
 460         PCI_DID_INTEL_TWL_GT1_2,
 461         0,
 462 };
 463
 464 static const struct pci_driver graphics_driver __pci_driver = {
 465         .ops            = &graphics_ops,
 466         .vendor         = PCI_VID_INTEL,
 467         .devices        = pci_device_ids,
 468 };