src/soc/intel/braswell/spi.c

   1 /*
   2  * Copyright (c) 2013 Google Inc.
   3  * Copyright (C) 2015 Intel Corp.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but without any warranty; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 /* This file is derived from the flashrom project. */
  17 #include <arch/io.h>
  18 #include <bootstate.h>
  19 #include <commonlib/helpers.h>
  20 #include <console/console.h>
  21 #include <delay.h>
  22 #include <device/pci_ids.h>
  23 #include <rules.h>
  24 #include <soc/lpc.h>
  25 #include <soc/pci_devs.h>
  26 #include <spi_flash.h>
  27 #include <spi-generic.h>
  28 #include <stdint.h>
  29 #include <compiler.h>
  30 #include <stdlib.h>
  31 #include <string.h>
  32
  33 #if ENV_SMM
  34 #define pci_read_config_byte(dev, reg, targ)\
  35         *(targ) = pci_read_config8(dev, reg)
  36 #define pci_read_config_word(dev, reg, targ)\
  37         *(targ) = pci_read_config16(dev, reg)
  38 #define pci_read_config_dword(dev, reg, targ)\
  39         *(targ) = pci_read_config32(dev, reg)
  40 #define pci_write_config_byte(dev, reg, val)\
  41         pci_write_config8(dev, reg, val)
  42 #define pci_write_config_word(dev, reg, val)\
  43         pci_write_config16(dev, reg, val)
  44 #define pci_write_config_dword(dev, reg, val)\
  45         pci_write_config32(dev, reg, val)
  46 #else /* ENV_SMM */
  47 #include <device/device.h>
  48 #include <device/pci.h>
  49 #define pci_read_config_byte(dev, reg, targ)\
  50         *(targ) = pci_read_config8(dev, reg)
  51 #define pci_read_config_word(dev, reg, targ)\
  52         *(targ) = pci_read_config16(dev, reg)
  53 #define pci_read_config_dword(dev, reg, targ)\
  54         *(targ) = pci_read_config32(dev, reg)
  55 #define pci_write_config_byte(dev, reg, val)\
  56         pci_write_config8(dev, reg, val)
  57 #define pci_write_config_word(dev, reg, val)\
  58         pci_write_config16(dev, reg, val)
  59 #define pci_write_config_dword(dev, reg, val)\
  60         pci_write_config32(dev, reg, val)
  61 #endif /* ENV_SMM */
  62
  63 typedef struct spi_slave ich_spi_slave;
  64
  65 static int ichspi_lock = 0;
  66
  67 typedef struct ich9_spi_regs {
  68         uint32_t bfpr;
  69         uint16_t hsfs;
  70         uint16_t hsfc;
  71         uint32_t faddr;
  72         uint32_t _reserved0;
  73         uint32_t fdata[16];
  74         uint32_t frap;
  75         uint32_t freg[5];
  76         uint32_t _reserved1[3];
  77         uint32_t pr[5];
  78         uint32_t _reserved2[2];
  79         uint8_t ssfs;
  80         uint8_t ssfc[3];
  81         uint16_t preop;
  82         uint16_t optype;
  83         uint8_t opmenu[8];
  84 } __packed ich9_spi_regs;
  85
  86 typedef struct ich_spi_controller {
  87         int locked;
  88
  89         uint8_t *opmenu;
  90         int menubytes;
  91         uint16_t *preop;
  92         uint16_t *optype;
  93         uint32_t *addr;
  94         uint8_t *data;
  95         unsigned int databytes;
  96         uint8_t *status;
  97         uint16_t *control;
  98 } ich_spi_controller;
  99
 100 static ich_spi_controller cntlr;
 101
 102 enum {
 103         SPIS_SCIP =             0x0001,
 104         SPIS_GRANT =            0x0002,
 105         SPIS_CDS =              0x0004,
 106         SPIS_FCERR =            0x0008,
 107         SSFS_AEL =              0x0010,
 108         SPIS_LOCK =             0x8000,
 109         SPIS_RESERVED_MASK =    0x7ff0,
 110         SSFS_RESERVED_MASK =    0x7fe2
 111 };
 112
 113 enum {
 114         SPIC_SCGO =             0x000002,
 115         SPIC_ACS =              0x000004,
 116         SPIC_SPOP =             0x000008,
 117         SPIC_DBC =              0x003f00,
 118         SPIC_DS =               0x004000,
 119         SPIC_SME =              0x008000,
 120         SSFC_SCF_MASK =         0x070000,
 121         SSFC_RESERVED =         0xf80000
 122 };
 123
 124 enum {
 125         HSFS_FDONE =            0x0001,
 126         HSFS_FCERR =            0x0002,
 127         HSFS_AEL =              0x0004,
 128         HSFS_BERASE_MASK =      0x0018,
 129         HSFS_BERASE_SHIFT =     3,
 130         HSFS_SCIP =             0x0020,
 131         HSFS_FDOPSS =           0x2000,
 132         HSFS_FDV =              0x4000,
 133         HSFS_FLOCKDN =          0x8000
 134 };
 135
 136 enum {
 137         HSFC_FGO =              0x0001,
 138         HSFC_FCYCLE_MASK =      0x0006,
 139         HSFC_FCYCLE_SHIFT =     1,
 140         HSFC_FDBC_MASK =        0x3f00,
 141         HSFC_FDBC_SHIFT =       8,
 142         HSFC_FSMIE =            0x8000
 143 };
 144
 145 enum {
 146         SPI_OPCODE_TYPE_READ_NO_ADDRESS =       0,
 147         SPI_OPCODE_TYPE_WRITE_NO_ADDRESS =      1,
 148         SPI_OPCODE_TYPE_READ_WITH_ADDRESS =     2,
 149         SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS =    3
 150 };
 151
 152 #if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH)
 153
 154 static u8 readb_(void *addr)
 155 {
 156         u8 v = read8(addr);
 157         printk(BIOS_DEBUG, "0x%p --> 0x%2.2x\n", addr, v);
 158         return v;
 159 }
 160
 161 static u16 readw_(void *addr)
 162 {
 163         u16 v = read16(addr);
 164         printk(BIOS_DEBUG, "0x%p --> 0x%4.4x\n", addr, v);
 165         return v;
 166 }
 167
 168 static u32 readl_(void *addr)
 169 {
 170         u32 v = read32(addr);
 171         printk(BIOS_DEBUG, "0x%p --> 0x%8.8x\n", addr, v);
 172         return v;
 173 }
 174
 175 static void writeb_(u8 b, void *addr)
 176 {
 177         printk(BIOS_DEBUG, "0x%p <-- 0x%2.2x\n", addr, b);
 178         write8(addr, b);
 179 }
 180
 181 static void writew_(u16 b, void *addr)
 182 {
 183         printk(BIOS_DEBUG, "0x%p <-- 0x%4.4x\n", addr, b);
 184         write16(addr, b);
 185 }
 186
 187 static void writel_(u32 b, void *addr)
 188 {
 189         printk(BIOS_DEBUG, "0x%p <-- 0x%8.8x\n", addr, b);
 190         write32(addr, b);
 191 }
 192
 193 #else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled  vvv NOT enabled */
 194
 195 #define readb_(a) read8(a)
 196 #define readw_(a) read16(a)
 197 #define readl_(a) read32(a)
 198 #define writeb_(val, addr) write8(addr, val)
 199 #define writew_(val, addr) write16(addr, val)
 200 #define writel_(val, addr) write32(addr, val)
 201
 202 #endif  /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */
 203
 204 static void write_reg(const void *value, void *dest, uint32_t size)
 205 {
 206         const uint8_t *bvalue = value;
 207         uint8_t *bdest = dest;
 208
 209         while (size >= 4) {
 210                 writel_(*(const uint32_t *)bvalue, bdest);
 211                 bdest += 4; bvalue += 4; size -= 4;
 212         }
 213         while (size) {
 214                 writeb_(*bvalue, bdest);
 215                 bdest++; bvalue++; size--;
 216         }
 217 }
 218
 219 static void read_reg(void *src, void *value, uint32_t size)
 220 {
 221         uint8_t *bsrc = src;
 222         uint8_t *bvalue = value;
 223
 224         while (size >= 4) {
 225                 *(uint32_t *)bvalue = readl_(bsrc);
 226                 bsrc += 4; bvalue += 4; size -= 4;
 227         }
 228         while (size) {
 229                 *bvalue = readb_(bsrc);
 230                 bsrc++; bvalue++; size--;
 231         }
 232 }
 233
 234 static ich9_spi_regs *spi_regs(void)
 235 {
 236         device_t dev;
 237         uint32_t sbase;
 238
 239 #if ENV_SMM
 240         dev = PCI_DEV(0, LPC_DEV, LPC_FUNC);
 241 #else
 242         dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
 243 #endif
 244         if (!dev) {
 245                 printk(BIOS_ERR, "%s: PCI device not found", __func__);
 246                 return NULL;
 247         }
 248
 249         pci_read_config_dword(dev, SBASE, &sbase);
 250         sbase &= ~0x1ff;
 251
 252         return (void *)sbase;
 253 }
 254
 255 void spi_init(void)
 256 {
 257         ich9_spi_regs *ich9_spi;
 258
 259         ich9_spi = spi_regs();
 260         if (!ich9_spi) {
 261                 printk(BIOS_ERR, "Not initialising spi as %s returned NULL\n",
 262                         __func__);
 263                 return;
 264         }
 265
 266         ichspi_lock = readw_(&ich9_spi->hsfs) & HSFS_FLOCKDN;
 267         cntlr.opmenu = ich9_spi->opmenu;
 268         cntlr.menubytes = sizeof(ich9_spi->opmenu);
 269         cntlr.optype = &ich9_spi->optype;
 270         cntlr.addr = &ich9_spi->faddr;
 271         cntlr.data = (uint8_t *)ich9_spi->fdata;
 272         cntlr.databytes = sizeof(ich9_spi->fdata);
 273         cntlr.status = &ich9_spi->ssfs;
 274         cntlr.control = (uint16_t *)ich9_spi->ssfc;
 275         cntlr.preop = &ich9_spi->preop;
 276 }
 277
 278 static void spi_init_cb(void *unused)
 279 {
 280         spi_init();
 281 }
 282
 283 BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL);
 284
 285 typedef struct spi_transaction {
 286         const uint8_t *out;
 287         uint32_t bytesout;
 288         uint8_t *in;
 289         uint32_t bytesin;
 290         uint8_t type;
 291         uint8_t opcode;
 292         uint32_t offset;
 293 } spi_transaction;
 294
 295 static inline void spi_use_out(spi_transaction *trans, unsigned int bytes)
 296 {
 297         trans->out += bytes;
 298         trans->bytesout -= bytes;
 299 }
 300
 301 static inline void spi_use_in(spi_transaction *trans, unsigned int bytes)
 302 {
 303         trans->in += bytes;
 304         trans->bytesin -= bytes;
 305 }
 306
 307 static void spi_setup_type(spi_transaction *trans)
 308 {
 309         trans->type = 0xFF;
 310
 311         /* Try to guess spi type from read/write sizes. */
 312         if (trans->bytesin == 0) {
 313                 if (trans->bytesout > 4)
 314                         /*
 315                          * If bytesin = 0 and bytesout > 4, we presume this is
 316                          * a write data operation, which is accompanied by an
 317                          * address.
 318                          */
 319                         trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
 320                 else
 321                         trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
 322                 return;
 323         }
 324
 325         if (trans->bytesout == 1) { /* and bytesin is > 0 */
 326                 trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
 327                 return;
 328         }
 329
 330         if (trans->bytesout == 4) { /* and bytesin is > 0 */
 331                 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
 332         }
 333
 334         /* Fast read command is called with 5 bytes instead of 4 */
 335         if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) {
 336                 trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
 337                 --trans->bytesout;
 338         }
 339 }
 340
 341 static int spi_setup_opcode(spi_transaction *trans)
 342 {
 343         uint16_t optypes;
 344         uint8_t opmenu[cntlr.menubytes];
 345
 346         trans->opcode = trans->out[0];
 347         spi_use_out(trans, 1);
 348         if (!ichspi_lock) {
 349                 /* The lock is off, so just use index 0. */
 350                 writeb_(trans->opcode, cntlr.opmenu);
 351                 optypes = readw_(cntlr.optype);
 352                 optypes = (optypes & 0xfffc) | (trans->type & 0x3);
 353                 writew_(optypes, cntlr.optype);
 354                 return 0;
 355         }
 356
 357         /* The lock is on. See if what we need is on the menu. */
 358         uint8_t optype;
 359         uint16_t opcode_index;
 360
 361         /* Write Enable is handled as atomic prefix */
 362         if (trans->opcode == SPI_OPCODE_WREN)
 363                 return 0;
 364
 365         read_reg(cntlr.opmenu, opmenu, sizeof(opmenu));
 366         for (opcode_index = 0; opcode_index < cntlr.menubytes;
 367                         opcode_index++) {
 368                 if (opmenu[opcode_index] == trans->opcode)
 369                         break;
 370         }
 371
 372         if (opcode_index == cntlr.menubytes) {
 373                 printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n",
 374                         trans->opcode);
 375                 return -1;
 376         }
 377
 378         optypes = readw_(cntlr.optype);
 379         optype = (optypes >> (opcode_index * 2)) & 0x3;
 380         if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS &&
 381                 optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS &&
 382                 trans->bytesout >= 3) {
 383                 /* We guessed wrong earlier. Fix it up. */
 384                 trans->type = optype;
 385         }
 386         if (optype != trans->type) {
 387                 printk(BIOS_DEBUG, "ICH SPI: Transaction doesn't fit type %d\n",
 388                         optype);
 389                 return -1;
 390         }
 391         return opcode_index;
 392 }
 393
 394 static int spi_setup_offset(spi_transaction *trans)
 395 {
 396         /* Separate the SPI address and data. */
 397         switch (trans->type) {
 398         case SPI_OPCODE_TYPE_READ_NO_ADDRESS:
 399         case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS:
 400                 return 0;
 401         case SPI_OPCODE_TYPE_READ_WITH_ADDRESS:
 402         case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS:
 403                 trans->offset = ((uint32_t)trans->out[0] << 16) |
 404                                 ((uint32_t)trans->out[1] << 8) |
 405                                 ((uint32_t)trans->out[2] << 0);
 406                 spi_use_out(trans, 3);
 407                 return 1;
 408         default:
 409                 printk(BIOS_DEBUG, "Unrecognized SPI transaction type %#x\n",
 410                         trans->type);
 411                 return -1;
 412         }
 413 }
 414
 415 /*
 416  * Wait for up to 400ms til status register bit(s) turn 1 (in case wait_til_set
 417  * below is True) or 0. In case the wait was for the bit(s) to set - write
 418  * those bits back, which would cause resetting them.
 419  *
 420  * Return the last read status value on success or -1 on failure.
 421  */
 422 static int ich_status_poll(u16 bitmask, int wait_til_set)
 423 {
 424         int timeout = 40000; /* This will result in 400 ms */
 425         u16 status = 0;
 426
 427         wait_til_set &= 1;
 428         while (timeout--) {
 429                 status = readw_(cntlr.status);
 430                 if (wait_til_set ^ ((status & bitmask) == 0)) {
 431                         if (wait_til_set)
 432                                 writew_((status & bitmask), cntlr.status);
 433                         return status;
 434                 }
 435                 udelay(10);
 436         }
 437
 438         printk(BIOS_ERR, "ICH SPI: SCIP timeout, read %x, expected %x\n",
 439                 status, bitmask);
 440         return -1;
 441 }
 442
 443 static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
 444                     size_t bytesout, void *din, size_t bytesin)
 445 {
 446         uint16_t control;
 447         int16_t opcode_index;
 448         int with_address;
 449         int status;
 450
 451         spi_transaction trans = {
 452                 dout, bytesout,
 453                 din, bytesin,
 454                 0xff, 0xff, 0
 455         };
 456
 457         /* There has to always at least be an opcode. */
 458         if (!bytesout || !dout) {
 459                 printk(BIOS_DEBUG, "ICH SPI: No opcode for transfer\n");
 460                 return -1;
 461         }
 462         /* Make sure if we read something we have a place to put it. */
 463         if (bytesin != 0 && !din) {
 464                 printk(BIOS_DEBUG, "ICH SPI: Read but no target buffer\n");
 465                 return -1;
 466         }
 467
 468         if (ich_status_poll(SPIS_SCIP, 0) == -1)
 469                 return -1;
 470
 471         writew_(SPIS_CDS | SPIS_FCERR, cntlr.status);
 472
 473         spi_setup_type(&trans);
 474         opcode_index = spi_setup_opcode(&trans);
 475         if (opcode_index < 0)
 476                 return -1;
 477         with_address = spi_setup_offset(&trans);
 478         if (with_address < 0)
 479                 return -1;
 480
 481         if (trans.opcode == SPI_OPCODE_WREN) {
 482                 /*
 483                  * Treat Write Enable as Atomic Pre-Op if possible
 484                  * in order to prevent the Management Engine from
 485                  * issuing a transaction between WREN and DATA.
 486                  */
 487                 if (!ichspi_lock)
 488                         writew_(trans.opcode, cntlr.preop);
 489                 return 0;
 490         }
 491
 492         /* Preset control fields */
 493         control = SPIC_SCGO | ((opcode_index & 0x07) << 4);
 494
 495         /* Issue atomic preop cycle if needed */
 496         if (readw_(cntlr.preop))
 497                 control |= SPIC_ACS;
 498
 499         if (!trans.bytesout && !trans.bytesin) {
 500                 /* SPI addresses are 24 bit only */
 501                 if (with_address)
 502                         writel_(trans.offset & 0x00FFFFFF, cntlr.addr);
 503
 504                 /*
 505                  * This is a 'no data' command (like Write Enable), its
 506                  * bytesout size was 1, decremented to zero while executing
 507                  * spi_setup_opcode() above. Tell the chip to send the
 508                  * command.
 509                  */
 510                 writew_(control, cntlr.control);
 511
 512                 /* wait for the result */
 513                 status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1);
 514                 if (status == -1)
 515                         return -1;
 516
 517                 if (status & SPIS_FCERR) {
 518                         printk(BIOS_ERR, "ICH SPI: Command transaction error\n");
 519                         return -1;
 520                 }
 521
 522                 return 0;
 523         }
 524
 525         /*
 526          * Check if this is a write command attempting to transfer more bytes
 527          * than the controller can handle. Iterations for writes are not
 528          * supported here because each SPI write command needs to be preceded
 529          * and followed by other SPI commands, and this sequence is controlled
 530          * by the SPI chip driver.
 531          */
 532         if (trans.bytesout > cntlr.databytes) {
 533                 printk(BIOS_DEBUG,
 534                 "ICH SPI: Too much to write. Does your SPI chip driver use"
 535                      " CONTROLLER_PAGE_LIMIT?\n");
 536                 return -1;
 537         }
 538
 539         /*
 540          * Read or write up to databytes bytes at a time until everything has
 541          * been sent.
 542          */
 543         while (trans.bytesout || trans.bytesin) {
 544                 uint32_t data_length;
 545
 546                 /* SPI addresses are 24 bit only */
 547                 writel_(trans.offset & 0x00FFFFFF, cntlr.addr);
 548
 549                 if (trans.bytesout)
 550                         data_length = min(trans.bytesout, cntlr.databytes);
 551                 else
 552                         data_length = min(trans.bytesin, cntlr.databytes);
 553
 554                 /* Program data into FDATA0 to N */
 555                 if (trans.bytesout) {
 556                         write_reg(trans.out, cntlr.data, data_length);
 557                         spi_use_out(&trans, data_length);
 558                         if (with_address)
 559                                 trans.offset += data_length;
 560                 }
 561
 562                 /* Add proper control fields' values */
 563                 control &= ~((cntlr.databytes - 1) << 8);
 564                 control |= SPIC_DS;
 565                 control |= (data_length - 1) << 8;
 566
 567                 /* write it */
 568                 writew_(control, cntlr.control);
 569
 570                 /* Wait for Cycle Done Status or Flash Cycle Error. */
 571                 status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1);
 572                 if (status == -1)
 573                         return -1;
 574
 575                 if (status & SPIS_FCERR) {
 576                         printk(BIOS_ERR, "ICH SPI: Data transaction error\n");
 577                         return -1;
 578                 }
 579
 580                 if (trans.bytesin) {
 581                         read_reg(cntlr.data, trans.in, data_length);
 582                         spi_use_in(&trans, data_length);
 583                         if (with_address)
 584                                 trans.offset += data_length;
 585                 }
 586         }
 587
 588         /* Clear atomic preop now that xfer is done */
 589         writew_(0, cntlr.preop);
 590
 591         return 0;
 592 }
 593
 594 static int xfer_vectors(const struct spi_slave *slave,
 595                         struct spi_op vectors[], size_t count)
 596 {
 597         return spi_flash_vector_helper(slave, vectors, count, spi_ctrlr_xfer);
 598 }
 599
 600 static const struct spi_ctrlr spi_ctrlr = {
 601         .xfer_vector = xfer_vectors,
 602         .max_xfer_size = member_size(ich9_spi_regs, fdata),
 603 };
 604
 605 const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
 606         {
 607                 .ctrlr = &spi_ctrlr,
 608                 .bus_start = 0,
 609                 .bus_end = 0,
 610         },
 611 };
 612
 613 const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);