src/vendorcode/amd/agesa/f14/Proc/GNB/Common/GnbPcie.h

   1 /* $NoKeywords:$ */
   2 /**
   3  * @file
   4  *
   5  * PCIe component definitions.
   6  *
   7  *
   8  *
   9  * @xrefitem bom "File Content Label" "Release Content"
  10  * @e project:     AGESA
  11  * @e sub-project: GNB
  12  * @e \$Revision: 38931 $   @e \$Date: 2010-10-01 15:50:05 -0700 (Fri, 01 Oct 2010) $
  13  *
  14  */
  15 /*
  16  *****************************************************************************
  17  *
  18  * Copyright (c) 2011, Advanced Micro Devices, Inc.
  19  * All rights reserved.
  20  *
  21  * Redistribution and use in source and binary forms, with or without
  22  * modification, are permitted provided that the following conditions are met:
  23  *     * Redistributions of source code must retain the above copyright
  24  *       notice, this list of conditions and the following disclaimer.
  25  *     * Redistributions in binary form must reproduce the above copyright
  26  *       notice, this list of conditions and the following disclaimer in the
  27  *       documentation and/or other materials provided with the distribution.
  28  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
  29  *       its contributors may be used to endorse or promote products derived
  30  *       from this software without specific prior written permission.
  31  *
  32  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  33  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  34  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  35  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
  36  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  37  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  38  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  39  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  40  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  41  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  42  *
  43  * ***************************************************************************
  44  *
  45  */
  46
  47 #ifndef _PCIEDEFS_H_
  48 #define _PCIEDEFS_H_
  49
  50 #pragma pack (push, 1)
  51
  52 #ifndef MAX_NUMBER_OF_COMPLEXES
  53   #define MAX_NUMBER_OF_COMPLEXES              1
  54 #endif
  55
  56 #define DESCRIPTOR_ALLOCATED                   0x40000000ull
  57 #define DESCRIPTOR_VIRTUAL                     0x20000000ull
  58 #define DESCRIPTOR_COMPLEX                     0x08000000ull
  59 #define DESCRIPTOR_SILICON                     0x04000000ull
  60 #define DESCRIPTOR_PCIE_WRAPPER                0x00400000ull
  61 #define DESCRIPTOR_DDI_WRAPPER                 0x00200000ull
  62 #define DESCRIPTOR_PCIE_ENGINE                 0x00040000ull
  63 #define DESCRIPTOR_DDI_ENGINE                  0x00020000ull
  64 #define DESCRIPTOR_ALL_WRAPPERS                (DESCRIPTOR_DDI_WRAPPER | DESCRIPTOR_PCIE_WRAPPER)
  65 #define DESCRIPTOR_ALL_ENGINES                 (DESCRIPTOR_DDI_ENGINE | DESCRIPTOR_PCIE_ENGINE)
  66
  67 #define UNUSED_LANE_ID                         128
  68
  69 #define IS_LAST_DESCRIPTOR(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_TERMINATE_LIST) == 0) : (1==1))
  70 #define IS_VALID_DESCRIPTOR(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_ALLOCATED) != 0) : (1==0))
  71
  72 // Get lowest PHY lane on engine
  73 #define PcieLibGetLoPhyLane(Engine) (Engine != NULL ? ((Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? Engine->EngineData.EndLane : Engine->EngineData.StartLane) : 0xFF)
  74 // Get highest PHY lane on engine
  75 #define PcieLibGetHiPhyLane(Engine) (Engine != NULL ? ((Engine->EngineData.StartLane > Engine->EngineData.EndLane) ? Engine->EngineData.StartLane : Engine->EngineData.EndLane) : 0xFF)
  76 // Get number of lanes on wrapper
  77 #define PcieLibWrapperNumberOfLanes(Wrapper) (Wrapper != NULL ? ((UINT8)(Wrapper->EndPhyLane - Wrapper->StartPhyLane + 1)) : 0)
  78 // Check if virtual descriptor
  79 #define PcieLibIsVirtualDesciptor(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_VIRTUAL) != 0) : (1==0))
  80 // Check if it is allocated descriptor
  81 #define PcieLibIsEngineAllocated(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_ALLOCATED) != 0) : (1==0))
  82 // Check if it is last descriptor in list
  83 #define PcieLibIsLastDescriptor(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_TERMINATE_LIST) != 0) : (1==1))
  84 // Check if descriptor a PCIe engine
  85 #define PcieLibIsPcieEngine(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_PCIE_ENGINE) != 0) : (1==0))
  86 // Check if descriptor a DDI engine
  87 #define PcieLibIsDdiEngine(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_DDI_ENGINE) != 0) : (1==0))
  88 // Check if descriptor a DDI wrapper
  89 #define PcieLibIsDdiWrapper(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_DDI_WRAPPER) != 0) : (1==0))
  90 // Check if descriptor a PCIe wrapper
  91 #define PcieLibIsPcieWrapper(Descriptor) (Descriptor != NULL ? ((Descriptor->Flags & DESCRIPTOR_PCIE_WRAPPER) != 0) : (1==0))
  92 // Check if descriptor a PCIe wrapper
  93 #define PcieLibGetNextDescriptor(Descriptor) (Descriptor != NULL ? (((Descriptor->Flags & DESCRIPTOR_TERMINATE_LIST) != 0) ? NULL : ((++Descriptor) != NULL ? Descriptor : NULL)) : NULL)
  94
  95
  96
  97 #define LANE_TYPE_PCIE_ALL                    0x0001
  98 #define LANE_TYPE_PCIE_ALLOCATED              0x0002
  99 #define LANE_TYPE_PCIE_ACTIVE                 0x0004
 100 #define LANE_TYPE_PCIE_SB                     0x0008
 101 #define LANE_TYPE_PCIE_HOTPLUG                0x0010
 102
 103 #define LANE_TYPE_PCIE_LANES                  0x000FFF
 104
 105 #define LANE_TYPE_DDI_ALL                     0x1000
 106 #define LANE_TYPE_DDI_ALLOCATED               0x2000
 107 #define LANE_TYPE_DDI_ACTIVE                  0x4000
 108
 109 #define LANE_TYPE_DDI_LANES                   0xFFF000
 110
 111 #define LANE_TYPE_ALL                         (LANE_TYPE_PCIE_ALL | LANE_TYPE_DDI_ALL)
 112 #define LANE_TYPE_ACTIVE                      (LANE_TYPE_PCIE_ACTIVE | LANE_TYPE_DDI_ACTIVE)
 113 #define LANE_TYPE_ALLOCATED                   (LANE_TYPE_PCIE_ALLOCATED | LANE_TYPE_DDI_ALLOCATED)
 114
 115 //typedef UINT64 PPCIe_ENGINE_CONFIG;
 116 //typedef UINT64 PPCIe_WRAPPER_CONFIG;
 117 //typedef UINT64 PPCIe_SILICON_CONFIG;
 118
 119 #define INIT_STATUS_PCIE_PORT_GEN2_RECOVERY          0x00000001ull
 120 #define INIT_STATUS_PCIE_PORT_BROKEN_LANE_RECOVERY   0x00000002ull
 121 #define INIT_STATUS_PCIE_PORT_TRAINING_FAIL          0x00000004ull
 122 #define INIT_STATUS_PCIE_TRAINING_SUCCESS            0x00000008ull
 123 #define INIT_STATUS_PCIE_EP_NOT_PRESENT              0x00000010ull
 124 #define INIT_STATUS_PCIE_PORT_IN_COMPLIANCE          0x00000020ull
 125 #define INIT_STATUS_DDI_ACTIVE                       0x00000040ull
 126 #define INIT_STATUS_ALLOCATED                        0x00000080ull
 127
 128 #define PCIE_PORT_GEN_CAP_BOOT                       0x00000001
 129 #define PCIE_PORT_GEN_CAP_MAX                        0x00000002
 130 #define PCIE_GLOBAL_GEN_CAP_ALL_PORTS                0x00000010
 131 #define PCIE_GLOBAL_GEN_CAP_TRAINED_PORTS            0x00000011
 132 #define PCIE_GLOBAL_GEN_CAP_HOTPLUG_PORTS            0x00000012
 133
 134 /// PCIe Link Training State
 135 typedef enum {
 136   PcieTrainingStandard,                                 ///< Standard training algorithm. Training contained to AmdEarlyInit.
 137                                                         ///< PCIe device accessible after AmdEarlyInit complete
 138   PcieTrainingDistributed,                              ///< Distribute training algorithm. Training distributed across AmdEarlyInit/AmdPostInit/AmdS3LateRestore
 139                                                         ///< PCIe device accessible after AmdPostInit complete.
 140                                                         ///< Algorithm potentially save up to 60ms in S3 resume time by skipping training empty slots.
 141 } PCIE_TRAINING_ALGORITHM;
 142
 143 /// PCIe port configuration info
 144 typedef struct {
 145   PCIe_PORT_DATA          PortData;                     ///< Port data
 146   UINT16                  StartCoreLane;                ///< Start Core Lane
 147   UINT16                  EndCoreLane;                  ///< End Core lane
 148   UINT8                   NativeDevNumber;              ///< Native PCI device number of the port
 149   UINT8                   NativeFunNumber;              ///< Native PCI function number of the port
 150   UINT8                   CoreId;                       ///< PCIe core ID
 151   UINT8                   PortId;                       ///< Port id on wrapper
 152   PCI_ADDR                Address;                      ///< PCI address of the port
 153   BOOLEAN                 IsSB;                         ///< Is it NB to SB link?
 154   UINT8                   State;                        ///< Training state
 155   UINT32                  TimeStamp;                    ///< Time stamp used to during training process
 156   UINT8                   GfxWrkRetryCount;             ///< Number of retry for GFX workaround
 157 } PCIe_PORT_CONFIG;
 158
 159 /// DDI (Digital Display Interface) configuration info
 160 typedef struct {
 161   PCIe_DDI_DATA           DdiData;                      ///< DDI Data
 162   UINT8                   DisplayPriorityIndex;         ///< Display priority index
 163   UINT8                   ConnectorId;                  ///< Connector id determined by enumeration
 164   UINT8                   DisplayDeviceId;              ///< Display device id determined by enumeration
 165 } PCIe_DDI_CONFIG;
 166
 167 /// Engine configuration data
 168 typedef struct {
 169   UINT32                  Flags;                        /**< Descriptor flags
 170                                                          * @li @b Bit31 - last descriptor on wrapper
 171                                                          * @li @b Bit30 - Descriptor allocated for PCIe port or DDI
 172                                                          */
 173   VOID                   *Wrapper;                      ///< Pointer to parent wrapper
 174   PCIe_ENGINE_DATA        EngineData;                   ///< Engine Data
 175   UINT32                  InitStatus;                   ///< Initialization Status
 176   UINT8                   Scratch;                      ///< Scratch pad
 177   union {
 178     PCIe_PORT_CONFIG      Port;                         ///< PCIe port configuration data
 179     PCIe_DDI_CONFIG       Ddi;                          ///< DDI configuration data
 180   } Type;
 181 } PCIe_ENGINE_CONFIG;
 182
 183 #define PcieEngineGetParentWrapper(mEnginerPtr) ((PCIe_WRAPPER_CONFIG *) (mEnginerPtr->Wrapper))
 184
 185 /// Wrapper configuration data
 186 typedef struct {
 187   UINT32                  Flags;                        /**< Descriptor flags
 188                                                          * @li @b Bit31 - last descriptor on silicon
 189                                                          */
 190   UINT8                   WrapId;                       ///< Wrapper ID
 191   UINT8                   NumberOfPIFs;                 ///< Number of PIFs on wrapper
 192   UINT8                   StartPhyLane;                 ///< Start PHY Lane
 193   UINT8                   EndPhyLane;                   ///< End PHY Lane
 194   UINT8                   StartPcieCoreId;              ///< Start PCIe Core ID
 195   UINT8                   EndPcieCoreId;                ///< End PCIe Core ID
 196   struct {
 197     UINT8                 PowerOffUnusedLanes:1;        ///< Power Off unused lanes
 198     UINT8                 PowerOffUnusedPlls:1;         ///< Power Off unused Plls
 199     UINT8                 ClkGating:1;                  ///< TXCLK gating
 200     UINT8                 LclkGating:1;                 ///< LCLK gating
 201     UINT8                 TxclkGatingPllPowerDown:1;    ///< TXCLK clock gating PLL power down
 202     UINT8                 PllOffInL1:1;                 ///< PLL off in L1
 203   } Features;
 204   VOID                   *EngineList;                   ///< Pointer to Engine list
 205   VOID                   *Silicon;                      ///< Pointer to parent silicon
 206   VOID                   *FmWrapper;                    ///< Pointer to family Specific configuration data
 207 } PCIe_WRAPPER_CONFIG;
 208
 209
 210 #define PcieWrapperGetEngineList(mWrapperPtr) ((PCIe_ENGINE_CONFIG *)(mWrapperPtr->EngineList))
 211 #define PcieWrapperGetParentSilicon(mWrapperPtr) ((PCIe_SILICON_CONFIG *)(mWrapperPtr->Silicon))
 212
 213 /// Silicon configuration data
 214 typedef struct  {
 215   UINT32                  Flags;                        /**< Descriptor flags
 216                                                          * @li @b Bit31 - last descriptor on complex
 217                                                          */
 218   PCI_ADDR                Address;                      ///< PCI address of GNB host bridge
 219   VOID                   *WrapperList;                  ///< Pointer to wrapper list
 220   VOID                   *FmSilicon;                    ///< Pointer to family Specific configuration data
 221 } PCIe_SILICON_CONFIG;
 222
 223 #define PcieSiliconGetWrapperList(mSiliconPtr) ((PCIe_WRAPPER_CONFIG *) (mSiliconPtr->WrapperList))
 224
 225 /// Complex configuration data
 226 typedef struct {
 227   UINT32                  Flags;                        /**< Descriptor flags
 228                                                          * @li @b Bit31 - last descriptor on platform
 229                                                          */
 230   UINT8                   SocketId;                     ///< Processor socket ID
 231   VOID                   *SiliconList;                  ///< Pointer to silicon list
 232 } PCIe_COMPLEX_CONFIG;
 233
 234 #define PcieComplexGetSiliconList(mComplexPtr) ((PCIe_SILICON_CONFIG *)(UINTN)((mComplexPtr)->SiliconList))
 235
 236 /// PCIe platform configuration info
 237 typedef struct {
 238   AMD_CONFIG_PARAMS      *StdHeader;                    ///< Standard configuration header
 239   UINT64                  This;                         ///< base structure Base
 240   UINT32                  LinkReceiverDetectionPooling; ///< Receiver pooling detection time in us.
 241   UINT32                  LinkL0Pooling;                ///< Pooling for link to get to L0 in us
 242   UINT32                  LinkGpioResetAssertionTime;   ///< Gpio reset assertion time in us
 243   UINT32                  LinkResetToTrainingTime;      ///< Time duration between deassert GPIO reset and release training in us                                                      ///
 244   UINT8                   GfxCardWorkaround;            ///< GFX Card Workaround
 245   UINT8                   PsppPolicy;                   ///< PSPP policy
 246   UINT8                   TrainingExitState;            ///< State at which training should exit (see PCIE_LINK_TRAINING_STATE)
 247   UINT8                   TrainingAlgorithm;            ///< Training algorithm (see PCIE_TRAINING_ALGORITHM)
 248   PCIe_COMPLEX_CONFIG     ComplexList[MAX_NUMBER_OF_COMPLEXES]; ///<
 249 } PCIe_PLATFORM_CONFIG;
 250
 251 /// PCIe Engine Description
 252 typedef struct {
 253   UINT32                  Flags;                        /**< Descriptor flags
 254                                                          * @li @b Bit31 - last descriptor on wrapper
 255                                                          * @li @b Bit30 - Descriptor allocated for PCIe port or DDI
 256                                                          */
 257   PCIe_ENGINE_DATA        EngineData;                 ///< Engine Data
 258 } PCIe_ENGINE_DESCRIPTOR;
 259
 260 /// PCIe Link Training State
 261 typedef enum {
 262   LinkStateResetAssert,                                 ///< Assert port GPIO reset
 263   LinkStateResetDuration,                               ///< Timeout for reset duration
 264   LinkStateResetExit,                                   ///< Deassert port GPIO reset
 265   LinkTrainingResetTimeout,                             ///< Port GPIO reset timeout
 266   LinkStateReleaseTraining,                             ///< Release link training
 267   LinkStateDetectPresence,                              ///< Detect device presence
 268   LinkStateDetecting,                                   ///< Detect link training.
 269   LinkStateBrokenLane,                                  ///< Check and handle broken lane
 270   LinkStateGen2Fail,                                    ///< Check and handle device that fail training if GEN2 capability advertised
 271   LinkStateL0,                                          ///< Device trained to L0
 272   LinkStateVcoNegotiation,                              ///< Check VCO negotiation complete
 273   LinkStateRetrain,                                     ///< Force retrain link.
 274   LinkStateTrainingFail,                                ///< Link training fail
 275   LinkStateTrainingSuccess,                             ///< Link training success
 276   LinkStateGfxWorkaround,                               ///< GFX workaround
 277   LinkStateCompliance,                                  ///< Link in compliance mode
 278   LinkStateDeviceNotPresent,                            ///< Link is not connected
 279   LinkStateTrainingCompleted                            ///< Link training completed
 280 } PCIE_LINK_TRAINING_STATE;
 281
 282 /// PCIe Port Visibility
 283 typedef enum {
 284   UnhidePorts,                                          ///< Command to unhide port
 285   HidePorts,                                            ///< Command to hide unused ports
 286 } PCIE_PORT_VISIBILITY;
 287
 288
 289 /// Table Register Entry
 290 typedef struct {
 291   UINT16          Reg;                                  ///< Address
 292   UINT32          Mask;                                 ///< Mask
 293   UINT32          Data;                                 ///< Data
 294 } PCIE_PORT_REGISTER_ENTRY;
 295
 296 /// Table Register Entry
 297 typedef struct {
 298   UINT32          Reg;                                  ///< Address
 299   UINT32          Mask;                                 ///< Mask
 300   UINT32          Data;                                 ///< Data
 301 } PCIE_HOST_REGISTER_ENTRY;
 302
 303 ///Link ASPM info
 304 typedef struct {
 305   PCI_ADDR        DownstreamPort;                       ///< PCI address of downstream port
 306   PCIE_ASPM_TYPE  DownstreamAspm ;                      ///< Downstream Device Aspm
 307   PCI_ADDR        UpstreamPort;                         ///< PCI address of upstream port
 308   PCIE_ASPM_TYPE  UpstreamAspm;                         ///< Upstream Device Capability
 309   PCIE_ASPM_TYPE  RequestedAspm;                        ///< Requested ASPM
 310 } PCIe_LINK_ASPM;
 311
 312 ///PCIe ASPM Latency Information
 313 typedef struct {
 314   UINT8  MaxL0sExitLatency;                             ///< Max L0s exit latency in us
 315   UINT8  MaxL1ExitLatency;                              ///< Max L1 exit latency in us
 316 } PCIe_ASPM_LATENCY_INFO;
 317
 318 /// PCI address association
 319 typedef struct {
 320   UINT8 NewDeviceAddress;                                ///< New PCI address (Device,Fucntion)
 321   UINT8 NativeDeviceAddress;                             ///< Native PCI address (Device,Fucntion)
 322 } PCI_ADDR_LIST;
 323
 324 /// The return status for GFX Card Workaround.
 325 typedef enum {
 326   GFX_WORKAROUND_DEVICE_NOT_READY,                       ///< GFX Workaround device is not ready.
 327   GFX_WORKAROUND_RESET_DEVICE,                           ///< GFX Workaround device need reset.
 328   GFX_WORKAROUND_SUCCESS                                 ///< The service completed normally.
 329 } GFX_WORKAROUND_STATUS;
 330
 331 /// GFX workaround control
 332 typedef enum {
 333   GfxWorkaroundDisable,                                  ///< GFX Workaround disabled
 334   GfxWorkaroundEnable                                    ///< GFX Workaround enabled
 335 } GFX_WORKAROUND_CONTROL;
 336
 337 /// PIF lane power state
 338 typedef enum {
 339   PifPowerStateL0,                                       ///<
 340   PifPowerStateLS1,                                      ///<
 341   PifPowerStateLS2,                                      ///<
 342   PifPowerStateOff = 0x7,                                ///<
 343 } PCIE_PIF_POWER_STATE;
 344
 345 /// PIF lane power control
 346 typedef enum {
 347   PowerDownPifs,                                        ///<
 348   PowerUpPifs                                           ///<
 349 } PCIE_PIF_POWER_CONTROL;
 350
 351 ///PLL rumup time
 352 typedef enum {
 353   NormalRampup,                                         ///<
 354   LongRampup,                                           ///<
 355 } PCIE_PLL_RAMPUP_TIME;
 356
 357 #pragma pack (pop)
 358
 359 #endif