src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/HY/F10HyMsrTables.c

   1 /* $NoKeywords:$ */
   2 /**
   3  * @file
   4  *
   5  * AMD Family_10 HY MSR tables with values as defined in BKDG
   6  *
   7  * @xrefitem bom "File Content Label" "Release Content"
   8  * @e project:      AGESA
   9  * @e sub-project:  CPU
  10  * @e \$Revision: 35136 $   @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
  11  *
  12  */
  13 /*
  14  *****************************************************************************
  15  *
  16  * Copyright (c) 2011, Advanced Micro Devices, Inc.
  17  * All rights reserved.
  18  *
  19  * Redistribution and use in source and binary forms, with or without
  20  * modification, are permitted provided that the following conditions are met:
  21  *     * Redistributions of source code must retain the above copyright
  22  *       notice, this list of conditions and the following disclaimer.
  23  *     * Redistributions in binary form must reproduce the above copyright
  24  *       notice, this list of conditions and the following disclaimer in the
  25  *       documentation and/or other materials provided with the distribution.
  26  *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
  27  *       its contributors may be used to endorse or promote products derived
  28  *       from this software without specific prior written permission.
  29  *
  30  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  31  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  32  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  33  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
  34  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  35  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  36  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  37  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  39  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * ***************************************************************************
  42  *
  43  */
  44
  45 /*----------------------------------------------------------------------------------------
  46  *                             M O D U L E S    U S E D
  47  *----------------------------------------------------------------------------------------
  48  */
  49 #include "AGESA.h"
  50 #include "cpuRegisters.h"
  51 #include "Table.h"
  52 #include "Filecode.h"
  53 CODE_GROUP (G1_PEICC)
  54 RDATA_GROUP (G1_PEICC)
  55
  56 #define FILECODE PROC_CPU_FAMILY_0X10_REVD_HY_F10HYMSRTABLES_FILECODE
  57
  58 /*----------------------------------------------------------------------------------------
  59  *                   D E F I N I T I O N S    A N D    M A C R O S
  60  *----------------------------------------------------------------------------------------
  61  */
  62
  63 /*----------------------------------------------------------------------------------------
  64  *                  T Y P E D E F S     A N D     S T R U C T U R E S
  65  *----------------------------------------------------------------------------------------
  66  */
  67
  68 /*----------------------------------------------------------------------------------------
  69  *           P R O T O T Y P E S     O F     L O C A L     F U N C T I O N S
  70  *----------------------------------------------------------------------------------------
  71  */
  72
  73 /*----------------------------------------------------------------------------------------
  74  *                          E X P O R T E D    F U N C T I O N S
  75  *----------------------------------------------------------------------------------------
  76  */
  77 STATIC CONST MSR_TYPE_ENTRY_INITIALIZER ROMDATA F10HyMsrRegisters[] =
  78 {
  79 //  M S R    T a b l e s
  80 // ----------------------
  81
  82 // MSR_LS_CFG (0xC0011020)
  83 // bit[1] = 0
  84   {
  85     MsrRegister,
  86     {
  87       AMD_FAMILY_10,                      // CpuFamily
  88       AMD_F10_GT_B0                       // CpuRevision
  89     },
  90     {AMD_PF_ALL},                           // platformFeatures
  91     {{
  92       MSR_LS_CFG,                           // MSR Address
  93       0x0000000000000000,                   // OR Mask
  94       (1 << 1)                              // NAND Mask
  95     }}
  96   },
  97
  98 // MSR_BU_CFG (0xC0011023)
  99 // bit[21] = 1
 100   {
 101     MsrRegister,
 102     {
 103       AMD_FAMILY_10,                      // CpuFamily
 104       AMD_F10_GT_B0                       // CpuRevision
 105     },
 106     {AMD_PF_ALL},                           // platformFeatures
 107     {{
 108       MSR_BU_CFG,                           // MSR Address
 109       (1 << 21),                            // OR Mask
 110       (1 << 21),                            // NAND Mask
 111     }}
 112   },
 113
 114 // MSR_BU_CFG2 (0xC001102A)
 115 // bit[50] = 1
 116 // For GH rev C1 and later [RdMmExtCfgQwEn]=1
 117   {
 118     MsrRegister,
 119     {
 120       AMD_FAMILY_10,                      // CpuFamily
 121       AMD_F10_GT_C0                       // CpuRevision
 122     },
 123     {AMD_PF_ALL},                           // platformFeatures
 124     {{
 125       MSR_BU_CFG2,                          // MSR Address
 126       0x0004000000000000,                   // OR Mask
 127       0x0004000000000000,                   // NAND Mask
 128     }}
 129   }
 130 };
 131
 132 CONST REGISTER_TABLE ROMDATA F10HyMsrRegisterTable = {
 133   AllCores,
 134   (sizeof (F10HyMsrRegisters) / sizeof (TABLE_ENTRY_FIELDS)),
 135   (TABLE_ENTRY_FIELDS *) &F10HyMsrRegisters,
 136 };
 137
 138